HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 435

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Relationship between Load and Store Instructions: When data is loaded from memory to the
destination register and the register is then specified as the source operand for a following store
instruction, the preceding instruction’s load is executed in the WB/DSP stage and the following
instruction’s store is executed in the MA stage. These stages are executed in exactly the same
cycle. Nevertheless, they do not contend. The CPU core and DSP unit use the same data transfer
method. In this case, when the data input to the internal bus is stored to the destination register, the
same data is simultaneously output again to the internal bus.
Figure 7.13 Relationship between CPU Core Operation Instructions and Store Instructions
Instruction 1 (MOV.L @Ra,Rn)
Instruction 2 (MOV.L Rn,@Rb)
Instruction 2 (MOV Rb,@Rc)
Instruction 1 (PADD X0,Y0,A0)
Instruction 2 (MOVX A0,@Ra)
Instruction 1 (ADD Ra,Rb)
Figure 7.12 Relationship between DSP Engine Operation Instructions and Store
Figure 7.14 Relationship between Load and Store Instructions in the CPU Core
Instruction 3
Instruction 4
Instruction 3
Instruction 4
Instruction 3
Instruction 4
IF
IF
IF
ID
IF
ID
IF
Instructions
ID
IF
EX
ID
IF
EX
ID
IF
EX
ID
IF
MA
EX
ID
IF
MA
EX
ID
IF
MA
EX
ID
IF
W/D
MA
EX
ID
W/D
Rev. 5.00 Jun 30, 2004 page 419 of 512
MA
EX
ID
W/D
—
—
—
W/D
MA W/D
EX
W/D
MA W/D
EX
MA
EX
ID
MA W/D
Section 7 Pipeline Operation
MA W/D
W/D
MA W/D
EX
MA W/D
REJ09B0171-0500O
: Slot
: Slot
: Slot