HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 221

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.1.35
Description: Transfers the source operand to the destination. This instruction is optimum for
accessing data in the peripheral module area. The data can be a byte, word, or longword, but only
the R0 register can be used.
A peripheral module base address is set to the GBR. When the peripheral module data is a byte,
the only change made is to zero-extend the 8-bit displacement. Consequently, an address within
+255 bytes can be specified. When the peripheral module data is a word, the 8-bit displacement is
zero-extended and doubled. Consequently, an address within +510 bytes can be specified. When
the peripheral module data is a longword, the 8-bit displacement is zero-extended and is
quadrupled. Consequently, an address within +1020 bytes can be specified. If the displacement is
too short to reach the memory operand, the above @(R0,Rn) mode must be used after the GBR
data is transferred to a general register. When the source operand is in memory, the loaded data is
stored in the register after it is sign-extended to a longword.
Note: The destination register of a data load is always R0. R0 cannot be accessed by the next
Format
MOV.B
@(disp,GBR),R0
MOV.W
@(disp,GBR),R0
MOV.L
@(disp,GBR),R0
MOV.B
R0,@(disp,GBR)
MOV.W
R0,@(disp,GBR)
MOV.L
R0,@(disp,GBR)
instruction until the load instruction is finished. The instruction order shown in figure 6.1
will give better results.
MOV (Move Peripheral Data): Data Transfer Instruction
Abstract
(disp + GBR)
extension
(disp
extension
(disp
R0
R0
R0
(disp + GBR)
(disp
(disp
2 + GBR)
4 + GBR)
R0
R0
2 + GBR)
4 + GBR)
sign
sign
R0
Code
11000100dddddddd
11000101dddddddd
11000110dddddddd
11000000dddddddd
11000001dddddddd
11000010dddddddd
Rev. 5.00 Jun 30, 2004 page 205 of 512
Section 6 Instruction Descriptions
Cycle
1
1
1
1
1
1
T
Bit
—
—
—
—
—
—
REJ09B0171-0500O
SH-1
Instructions
Applicable
SH-2
SH-
DSP