HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 74

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
When the S bit of the SR register is set to 1, the overflow prevention function (saturation
operation) is engaged. The overflow prevention function can be specified for ALU integer
arithmetic operations executed by the DSP unit. When the operation result overflows, the
maximum (positive) or minimum (negative) value is stored.
4.9
4.9.1
ALU logical operations are performed between registers. The source and destination operands are
selected independently from the DSP register. These operations use only the top word of the
respective operands. The bottom word of the source operand and the guard bits are ignored and the
bottom word of the destination operand and guard bits are cleared with zeros. These operations are
executed in the DSP stage (the last stage) of the pipeline.
Whenever an ALU arithmetic operation is executed, the DSR register’s DC, N, Z, V, and GT bits
are basically updated by the operation result. For conditional instructions, condition bits and flags
are not updated even when the specified condition is achieved and the instruction executed. For
unconditional instructions, the bits are always updated according to the operation result. The DC
bit is updated as specified in the CS bits. Figure 4.12 shows the ALU logical operation flowchart.
Rev. 5.00 Jun 30, 2004 page 58 of 512
REJ09B0171-0500O
Guard bits
ALU Logical Operations
Function
31
Source 1
Figure 4.12 ALU Logical Operation Flowchart
Guard bits
Destination
31
0
Guard bits
ALU
31
Source 2
0
GT
Z
DSR
N
0
V
: Ignored
: Cleared to 0
DC