HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 52

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
arithmetic shifts, and logical shifts. or MSB detection instructions and rounding instructions, set
the condition bits like for arithmetic operations.
Arithmetic operations include overflow preventing instructions (saturation operations). When
saturation operation is specified with the S bit in the SR register, the maximum (positive) or
minimum (negative) value is stored when the result of operation overflows.
4.5
The DSP command performs two different types of memory accesses. One uses the X and Y data
transfer instructions (MOVX.W and MOVY.W) while the other uses the single data transfer
instructions (MOVS.W and MOVS.L). Data addressing for these two types of instructions also
differs. Table 4.9 summarizes the data transfer instructions.
Table 4.9
Item
Address registers
Index registers
Addressing
Modulo addressing
Data buses
Data length
Bus contention
Memory
Source registers
Destination registers
Rev. 5.00 Jun 30, 2004 page 36 of 512
REJ09B0171-0500O
DSP Data Addressing
Summary of Data Transfer Instructions
X and Y Data Transfer
Processing (MOVX.W and
MOVY.W)
Ax: R4, R5; Ay: R6, R7
Ix: R8; Iy: R9
Nop/Inc(+2)/Index addition:
Post-increment
—
Available
XDB, YDB
16 bits (word)
None
X and Y data memories
Da: A0, A1
Dx: X0/X1; Dy: Y0/Y1
Single Data Transfer Processing
(MOVS.W and MOVS.L)
As: R2, R3, R4, R5
Is: R8
Nop/Inc(+2, +4)/Index addition:
Post-increment
Dec(–2, –4): Pre-decrement
Not available
IDB
16 or 32 bits (word or longword)
Occurs
All memory spaces
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G