HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 41

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.1
All instructions are RISC type. Their features are detailed in this section.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program coding efficiency.
One Instruction/Cycle: Basic instructions can be executed in one cycle using the pipeline system.
Instructions are executed in 50 ns at 20 MHz, in 35 ns at 28.7MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
calculated with longword data (table 4.1). Immediate data is sign-extended for arithmetic
operations or zero-extended for logic operations. It also is calculated with longword data.
Table 4.1
Note: The address of the immediate data is accessed by @(disp, PC).
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed. Pipeline disruption
during branching is reduced by first executing the instruction that follows the branch instruction,
and then branching (table 4.2). With delayed branching, branching occurs after execution of the
slot instruction. However, instructions such as register changes etc. are executed in the order of
delayed branch instruction, then delay slot instruction. For example, even if the register in which
the branch destination address has been loaded is changed by the delay slot instruction, the branch
will still be made using the value of the register prior to the change as the branch destination
address.
SH-1/SH-2/SH-DSP CPU
MOV.W
ADD
.DATA.W H'1234
.........
RISC-Type Instruction Set
@(disp,PC),R1
R1,R0
Sign Extension of Word Data
Section 4 Instruction Features
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Rev. 5.00 Jun 30, 2004 page 25 of 512
Example for Other CPU
ADD.W
Section 4 Instruction Features
#H'1234,R0
REJ09B0171-0500O