HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 163

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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6.1.11
Description: Branches to the subroutine procedure at a specified address after executing the
instruction following this BSRF instruction. The PC value is stored in the PR. The branch
destination is PC + the 32-bit contents of the general register Rm. However, in this case it is used
for address calculation. The PC is the address 4 bytes after this instruction. Used as a subroutine
procedure call in combination with RTS.
Note: Since this is a delayed branch instruction, the instruction after BSR is executed before
Operation:
Format
BSRF Rm
BSRF(long m) /* BSRF Rm */
{
}
PR=PC+Is_32bit_Inst(PR+2);
PC+=R[m];
Delay_Slot(PR+2);
branching. No interrupts and address errors are accepted between this instruction and the
next instruction. If the next instruction is a branch instruction, it is acknowledged as an
illegal slot instruction.
BSRF (Branch to Subroutine Far): Branch Instruction
Abstract
PC
Rm + PC
PR,
PC
Code
0000mmmm00000011 2
Rev. 5.00 Jun 30, 2004 page 147 of 512
Cycle T Bit SH-1 SH-2
Section 6 Instruction Descriptions
REJ09B0171-0500O
Instructions
Applicable
SH-
DSP

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