HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 161

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.1.10
Description: Branches to the subroutine procedure at a specified address. The PC value is stored
in the PR, and the program branches to an address specified by PC + displacement However, in
this case it is used for address calculation. The PC is the address 4 bytes after this instruction. The
12-bit displacement is sign-extended and doubled. Consequently, the relative interval from the
branch destination is –4096 to +4094 bytes. If the displacement is too short to reach the branch
destination, the JSR instruction must be used instead. With JSR, the destination address must be
transferred to a register by using the MOV instruction. This BSR instruction and the RTS
instruction are used together for a subroutine procedure call.
Note: Since this is a delayed branch instruction, the instruction after BSR is executed before
Operation:
Format
BSR
BSR(long d)
{
}
long disp;
if ((d&0x800)==0) disp=(0x00000FFF & (long) d);
else disp=(0xFFFFF000 | (long) d);
PR=PC+Is_32bit_Inst(PR+2);
PC=PC+(disp<<1);
Delay_Slot(PR+2);
label
branching. No interrupts and address errors are accepted between this instruction and the
next instruction. If the next instruction is a branch instruction, it is acknowledged as an
illegal slot instruction.
BSR (Branch to Subroutine): Branch Instruction
/* BSR disp */
Abstract
PC
PR, disp
2+ PC
PC
Code
1011dddddddddddd
Rev. 5.00 Jun 30, 2004 page 145 of 512
Section 6 Instruction Descriptions
REJ09B0171-0500O
Cycle
2
T Bit
—