HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 50

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 4 Instruction Features
Instruction Formats
nmd format
15
d format
15
d12 format
15
nd8 format
15
i format
15
ni format
15
Note: Applies to the SH-2 and SH-DSP. The BRAF instruction is not supported by the SH-1.
Rev. 5.00 Jun 30, 2004 page 34 of 512
REJ09B0171-0500O
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
dddd
nnnn
nnnn
nnnn
xxxx
xxxx
mmmm
dddd
dddd
dddd
i i i i
i i i i
dddd
dddd
dddd
dddd
i i i i
i i i i
0
0
0
0
0
0
Source
Operand
mmmm: Direct
register
mmmmdddd:
Indirect register
with
displacement
dddddddd:
Indirect GBR
with
displacement
R0(Direct
register)
dddddddd: PC
relative with
displacement
dddddddd: PC
relative
dddddddddddd:
PC relative
dddddddd: PC
relative with
displacement
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
Indirect indexed
R0 (Direct register) AND
Destination
Operand
nnnndddd: Indirect
register with
displacement
nnnn: Direct
register
R0 (Direct register) MOV.L
dddddddd: Indirect
GBR with
displacement
R0 (Direct register) MOVA
—
—
nnnn: Direct
register
GBR
—
nnnn: Direct
register
Example
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
@(disp,GBR),R0
MOV.L
R0,@(disp,GBR)
@(disp,PC),R0
BF
BRA
(label = disp
+ PC)
MOV.L
@(disp,PC),Rn
AND.B
#imm,@(R0,GBR)
TRAPA
ADD
label
label
#imm,R0
#imm
#imm,Rn