HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 198

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Section 6 Instruction Descriptions
6.1.29
Format
LDRS @(disp,PC) disp
Description: Stores the effective address of the source operand in the repeat start register RS. The
effective address is an address specified by PC + displacement. The PC is the address four bytes
after this instruction. The 8-bit displacement is sign-extended and doubled. Consequently, the
relative interval from the branch destination is –256 to +254 bytes.
Note: When the instructions of the repeat (loop) program are below 3, the effective address value
Operation:
Rev. 5.00 Jun 30, 2004 page 182 of 512
REJ09B0171-0500O
LDRS(long d) /* LDRS @(disp, PC) */
{
}
long disp;
if ((d&0x80)==0) disp=(0x000000FF & (long)d);
else disp=(0xFFFFFF00 | (long)d);
RS=PC+(disp<<1);
PC+=2;
designated for the RS register is different from the actual repeat start address. Refer to
table 4.35. "RS and RE setting rule", for more information. If this instruction is arranged
immediately after the delayed branch instruction, the PC becomes "the first address +2" of
the branch destination.
LDRS (Load Effective Address to RS Register): System Control Instruction
Abstract
RS
2 + PC
Code
10001100dddddddd 1
Cycle T Bit SH-1 SH-2
Instructions
Applicable
SH-
DSP

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