HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 505

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Unconditional Branch Instructions (Common, or SH-2 CPU, SH-DSP): Include the following
instruction types:
The pipeline has three stages: IF, ID, and EX (figure 7.82). Unconditionally branched instructions
are delay branched. The branch destination address is calculated in the EX stage. The instruction
following the unconditional branch instruction (instruction A), that is, the delay slot instruction is
not fetched and discarded as conditional branch instructions are, but is instead executed. Note that
the ID slot of the delay slot instruction does stall for one cycle. The branch destination instruction
starts its fetch from the slot after the slot that has the EX stage of instruction A.
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
Branch destination
label
Rm (SH-2, SH-DSP CPU)
label
Rm (SH-2, SH-DSP CPU)
@Rm
@Rm
Instruction A
Delay slot
Figure 7.82 Unconditional Branch Instruction Pipeline
.....
.....
IF
ID
IF
EX
—
ID
IF
EX MA WB
ID
IF
Rev. 5.00 Jun 30, 2004 page 489 of 512
EX
ID
EX
.....
Section 7 Pipeline Operation
.....
REJ09B0171-0500O
: Slot