HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 162

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
Example:
Rev. 5.00 Jun 30, 2004 page 146 of 512
REJ09B0171-0500O
TRGET:
Note: With delayed branching, branching occurs after execution of the slot instruction.
However, instructions such as register changes etc. are executed in the order of delayed
branch instruction, then delay slot instruction. For example, even if the register in which
the branch destination address has been loaded is changed by the delay slot instruction,
the branch will still be made using the value of the register prior to the change as the
branch destination address.
BSR
MOV
ADD
.......
.......
MOV
RTS
MOV
TRGET
R3,R4
R0,R1
R2,R3
#1,R0
;
;
;
address of the BSR instruction (return address for when the
subroutine procedure is completed (PR data))
;
;
; Returns to the above ADD instruction
; Executes MOV before branching
Branches to TRGET
Executes the MOV instruction before branching
The PC location is used to calculate the branch destination
Procedure entrance