HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 456

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
Multiply/Accumulate Instruction (SH-1 CPU): Includes the following instruction type:
MAC.W
@Rm+, @Rn+
: Slot
Instruction A
IF
ID
EX
MA
MA
mm
mm
Next instruction
IF
—
ID
EX
MA
WB
Third instruction in series
IF
ID
EX
MA
WB
......
Figure 7.23 Multiply/Accumulate Instruction Pipeline
The pipeline has seven stages: IF, ID, EX, MA, MA, mm, and mm. The second MA reads the
memory and accesses the multiplier. mm indicates that the multiplier is operating. mm operates for
two cycles after the final MA ends, regardless of slot. The ID of the instruction after the MAC.W
instruction is stalled for 1 slot. The two MAs of the MAC.W instruction, when they contend with
IF, split the slots as described in Section 7.2.1, Contention between Instruction Fetch (IF) and
Memory Access (MA).
When an instruction that does not use the multiplier comes after the MAC.W instruction, the
MAC.W instruction may be considered to be a five-stage pipeline instruction of IF, ID, EX, MA,
MA. In such cases, the ID of the next instruction simply stalls one slot and thereafter operates like
a normal pipeline. When an instruction that uses the multiplier comes after the MAC.W
instruction, however, contention occurs with the multiplier, so operation is different from normal.
This occurs in the following cases:
1. When a MAC.W instruction is located immediately after another MAC.W instruction
2. When a MULS.W instruction is located immediately after a MAC.W instruction
3. When an STS (register) instruction is located immediately after a MAC.W instruction
4. When an STS.L (memory) instruction is located immediately after a MAC.W instruction
5. When an LDS (register) instruction is located immediately after a MAC.W instruction
6. When an LDS.L (memory) instruction is located immediately after a MAC.W instruction
Rev. 5.00 Jun 30, 2004 page 440 of 512
REJ09B0171-0500O