HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 87

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.12.4
The condition bits are set as follows.
4.13
4.13.1
The DSP unit has a function for rounding 32-bit values to 16-bit values. When the value has guard
bits, 40 bits are rounded to 24 bits. When the rounding instruction is executed, H'0000 8000 is
added to the source operand and the bottom word is then cleared to zeros.
Rounding uses all bits of the source and destination operands. The action of the operation is the
same as for fixed decimal point operations and is executed in the DSP stage (the last stage) of the
pipeline.
The rounding instruction is unconditional. The DSR register’s DC, N, Z, V, and GT bits are thus
always updated according to the operation result.
Figure 4.17 shows the rounding flowchart. Figure 4.18 shows the rounding process definitions.
The N bit is the same as the result of the ALU integer operation. It is set to 1 for a negative
operation result and 0 for a positive operation result.
The Z bit is the same as the result of the ALU integer operation. It is set to 1 when the
operation result is zero; otherwise, the Z bit is 0.
The V bit is always 0.
The GT bit is the same as the result of the ALU integer operation. It is set 1 for a positive
operation result and otherwise to 0.
Operation Function
Condition Bits
Rounding
Rev. 5.00 Jun 30, 2004 page 71 of 512
Section 4 Instruction Features
REJ09B0171-0500O