HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 201

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Note: No interrupts are accepted between this instruction and the next instruction. Address errors
For the SH-1 CPU, the lower 10 bits are stored in MACH. For the SH-2 and SH-DSP CPU, 32 bits
are stored in MACH.
Operation:
LDSMACH(long m)
{
}
LDSMACL(long m)
{
}
LDSPR(long m)
{
}
LDSDSR(long m)
{
}
LDSA0(long m)
{
}
MACH=R[m];
if ((MACH&0x00000200)==0) MACH&=0x000003FF;
else MACH|=0xFFFFFC00;
MACL=R[m];
PC+=2;
PR=R[m];
PC+=2;
DSR=R[m]&0x0000000F;
PC+=2;
A0=R[m];
if((A0&0x80000000)==0) A0G=0x00;
else A0G=0xFF;
PC+=2;
are accepted.
PC+=2; N
/* LDS Rm,MACH */
/* LDS Rm,MACL */
/* LDS Rm,PR */
/* LDS Rm,DSR */
/* LDS Rm,A0 */
Rev. 5.00 Jun 30, 2004 page 185 of 512
Section 6 Instruction Descriptions
For SH-1 CPU(these 2 lines
not needed for SH-2 and V
SH-DSP CPU)
REJ09B0171-0500O

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