HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 19

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 1.2
Feature
DSP unit
DSP registers
DSP data b1us
Parallel processing
Address operator
DSP data addressing
modes
Repeat control
Instruction set
Pipeline
Features of SH-DSP Series Microprocessor CPUs
Description
1 cycle multiplier
16 bits
Arithmetic logic unit (ALU)
Barrel shifter
DSP registers
MSB detection
Two 40-bit data registers
Six 32-bit data registers
DSP status register (DSR)
Modulo register (MOD, 32 bits) added to control registers
Repeat counter (RC) added to status registers (SR)
Repeat start register (RS) and repeat end register (RE) added to
control registers
Expanded Harvard architecture
Simultaneous access of two data bus and one instruction bus
Maximum of four parallel processes (ALU operation, multiplication,
and two loads or stores)
Two address operators
Address operations for accessing two memories
Increment, decrement and index
Increment, decrement and index can have modulo addressing or
not
Zero-overhead repeat control (loop)
16 or 32 bits
SuperH microprocessor instructions added for accessing DSP
registers.
Five-stage pipeline
Fifth stage is both the WB stage and the DSP stage.
16 bits (for load or store only)
32 bits (including for ALU operations and multiplication)
16 bits
32 bits (fixed decimal point)
Rev. 5.00 Jun 30, 2004 page 3 of 512
REJ09B0171-0500O
Section 1 Features