HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 11

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2
5.3
Section 6 Instruction Descriptions
6.1
5.1.4
5.1.5
5.1.6
5.1.7
DSP Data Transfer Instruction Set .................................................................................... 111
5.2.1
5.2.2
5.2.3
DSP Operation Instruction Set .......................................................................................... 115
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Instruction Descriptions .................................................................................................... 127
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10 BSR (Branch to Subroutine): Branch Instruction................................................. 145
6.1.11 BSRF (Branch to Subroutine Far): Branch Instruction ........................................ 147
6.1.12 BT (Branch if True): Branch Instruction.............................................................. 149
6.1.13 BT/S (Branch if True with Delay Slot): Branch Instruction ................................ 151
6.1.14 CLRMAC (Clear MAC Register): System Control Instruction ........................... 153
6.1.15 CLRT (Clear T Bit): System Control Instruction................................................. 154
6.1.16 CMP/cond (Compare Conditionally): Arithmetic Instruction.............................. 155
6.1.17 DIV0S (Divide Step 0 as Signed): Arithmetic Instruction................................... 159
6.1.18 DIV0U (Divide Step 0 as Unsigned): Arithmetic Instruction .............................. 160
6.1.19 DIV1 (Divide 1 Step): Arithmetic Instruction ..................................................... 161
6.1.20 DMULS.L (Double-Length Multiply as Signed): Arithmetic Instruction ........... 166
6.1.21 DMULU.L (Double-Length Multiply as Unsigned): Arithmetic Instruction....... 168
6.1.22 DT (Decrement and Test): Arithmetic Instruction ............................................... 170
Shift Instructions.................................................................................................. 103
Branch Instructions .............................................................................................. 104
System Control Instructions................................................................................. 105
CPU Instructions That Support DSP Functions ................................................... 108
Double Data Transfer Instructions (X Memory Data) ......................................... 112
Double Data Transfer Instructions (Y Memory Data) ......................................... 112
Single Data Transfer Instructions......................................................................... 113
ALU Arithmetic Operation Instructions .............................................................. 118
ALU Logical Operation Instructions ................................................................... 122
Fixed Decimal Point Multiplication Instructions ................................................. 122
Shift Operation Instructions ................................................................................. 123
System Control Instructions................................................................................. 124
NOPX and NOPY Instruction Code .................................................................... 125
Sample Description (Name): Classification......................................................... 127
ADD (ADD Binary): Arithmetic Instruction ....................................................... 131
ADDC (ADD with Carry): Arithmetic Instruction .............................................. 132
ADDV (ADD with V Flag Overflow Check): Arithmetic Instruction................. 133
AND (AND Logical): Logic Operation Instruction ............................................. 135
BF (Branch if False): Branch Instruction............................................................. 137
BF/S (Branch if False with Delay Slot): Branch Instruction................................ 139
BRA (Branch): Branch Instruction ...................................................................... 141
BRAF (Branch Far): Branch Instruction.............................................................. 143
.................................................................................. 127
Rev. 5.00 Jun 30, 2004 page ix of xiv
REJ09B0171-0500O