HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 442

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
7.4
This section describes the operation of the instruction pipelines. By combining these with the rules
described so far, the way pipelines flow in a program and the number of instruction execution
cycles can be calculated.
In the following figures, “Instruction A” refers to the instruction being discussed. When “IF” is
written in the instruction fetch stage, it may refer to either “IF” or “if”. When there is contention
between IF and MA, the slot will split, but the manner of the split is not discussed in the tables,
with a few exceptions. When a slot has split, see section 7.2.1, Contention between Instruction
Fetch (IF) and Memory Access (MA). Base your response on the rules for pipeline operation given
there.
Table 7.2 shows the number of instruction stages and number of execution cycles as follows:
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Type: Given by function
Category: Categorized by differences in instruction operation
Stages: The number of stages in the instruction
Cycles: The number of execution cycles when there is no contention
Contention: Indicates the contention that occurs
Instructions: Gives a mnemonic for the instruction concerned
Operation of Instruction Pipelines