HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 293

IC H8 MCU FLASH 256K 100TQFP

HD64F7047F50V

Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Datasheets

Specifications of HD64F7047F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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6.2.4
Description: Transfers the source operand data to the destination. Transfer can be from memory
to register or register to memory. The transferred data can be a word or longword. When a word is
transferred, the source operand is in memory, and the destination operand is a register, the word
data is loaded to the top word of the register and the bottom word is cleared with zeros. When the
Format
MOVS.W
@-As,Ds
MOVS.W
@As,Ds
MOVS.W
@As+,Ds
MOVS.W
@As+Ix,Ds
MOVS.W
Ds,@-As
MOVS.W
Ds,@As
MOVS.W
Ds,@As+
MOVS.W
Ds,@As+Ix
MOVS.L
@-As,Ds
MOVS.L
@As,Ds
MOVS.L
@As+,Ds
MOVS.L
@As+Ix,Ds
MOVS.L Ds,@-
As
MOVS.L
Ds,@As
MOVS.L
Ds,@As+
MOVS.L
Ds,@As+Ix
MOVS (Move Single Data between Memory and DSP Register): DSP Data
Transfer Instruction
Abstract
As–2 As,(As) MSW of
Ds,0 LSW of Ds
(As) MSW of Ds,0 LSW of
Ds
(As) MSW of Ds,0 LSW of
Ds, As+2 As
(As) MSW of Ds,0 LSW of
Ds, As+Ix As
As–2 As,MSW of Ds (As)
MSW of Ds (As)
MSW of Ds (As),As+2 As
MSW of Ds (As),As+Ix As
As–4 As,(As) Ds
(As) Ds
(As) Ds,As+4 As
(As) Ds,As+Ix As
As–4 As,Ds (As)
Ds (As)
Ds (As),As+4 As
Ds (As),As+Ix As
111101AADDDD0000
111101AADDDD0100
111101AADDDD1000
111101AADDDD1100
111101AADDDD0001
111101AADDDD0101
111101AADDDD1001
111101AADDDD1101
111101AADDDD0010
111101AADDDD0110
111101AADDDD1010
111101AADDDD1110
111101AADDDD0011
111101AADDDD0111
111101AADDDD1011
111101AADDDD1111
Code
Rev. 5.00 Jun 30, 2004 page 277 of 512
Section 6 Instruction Descriptions
Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DC
Bit
REJ09B0171-0500O
SH-1
Instructions
Applicable
SH-2
SH-
DSP

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