MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 979

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Figure 16-26

Figure 16-27

This section addresses some of the limitations and restrictions of the DMA controller and is intended to

help software maximize the DMA performance and avoid DMA programming errors.

The limitations of the DMA controller are the following:

The DMA controller restrictions are as follows:

Freescale Semiconductor

Due to the limited number of buffers that the DMA controller can use, stride sizes less than 64 bytes

should be avoided. Maximum utilization is obtained from strides greater than or equal to 256 bytes.

However, small stride sizes can be used for scatter-gather functions.

Coherent reads or writes are broken up into cache line accesses in the DMA.

All interface capabilities from where descriptors are being fetched must support read sizes of 32

bytes or greater.

If MRn[SAHE] is set, the source interface transfer size capability must be greater than or equal to

MRn[SAHTS]. The source address must be aligned to a size specified by SAHTS.

Limitations and Restrictions

describes the format of the list descriptors.

describes the format of the link descriptors.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Figure 16-27. Link Descriptor Format

Figure 16-26. List Descriptor Format

First Link Descriptor Extended Address

Next Link Descriptor Extended Address

Next List Descriptor Extended Address

Next Link Descriptor Address

First Link Descriptor Address

Next List Descriptor Address

Destination Attributes

Destination Address

Destination Stride

Source Attributes

Source Address

Source Stride

DMA Controller