MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1074

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Figure 18-13
18.3.5.1.1
The PCI Express outbound translation address registers, shown in
addresses in the system address space for window hits within the PCI Express outbound address translation
windows. The new translated address is created by concatenating the transaction offset to this translation
address.
Table 18-15
18-20
12–31
0–11
Bits
From Memory
Offset Window 0: 0xC00
Reset
Name
TEA
TA
W
R
Figure 18-14. PCI Express Outbound Translation Address Registers (PEXOTAR n )
describes the fields of the PCI Express outbound translation address registers.
shows the outbound transaction flow.
Window 1: 0xC20
Window 2: 0xC40
Window 3: 0xC60
Window 4: 0xC80
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
PCI Express Outbound Translation Address Registers (PEXOTAR n )
Translation extended address. System address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the size field. Corresponds to PCI Express
address bits [43:32] (bit 32 is the lsb).
Translation address. System address which indicates the starting point of the outbound translated address.
The translation address must be aligned based on the size field. This corresponds to PCI Express address
bits [31:12].
Outbound ATMUs
TEA
Figure 18-13. RC Outbound Transaction Flow
Table 18-15. PEXOTAR n Field Descriptions
Prefetchable Memory Limit
Memory or IO Base
Memory or IO Limit
11 12
Primary Side
Memory Base
Prefetchable
All zeros
Description
Figure
TA
18-14, select the starting
Access: Read/Write
Freescale Semiconductor
Secondary Side
31