MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1258

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug Features and Watchpoint Facility
21.4.5
The trace buffer is a 256 × 64 array that can capture information about the internal processing of
transactions to selected interfaces. The trace buffer controls are a superset of those for the watchpoint
monitor. Close inspection of the trace buffer control registers (TBCRn) and the WM control registers
(WMCRn) shows that trace buffer controls not needed for the WM are marked reserved in WMCRn. This
permits using the trace buffer as a second watchpoint monitor by simply ignoring the trace options.
The trace buffer provides great flexibility about when to start tracing, when to stop tracing, and what to
trace. The trace mode field, TBCR0[MODE], indicates when to trace: on every valid cycle, on a
watchpoint monitor event, or when all the programmed events in the TBCR are met. This permits a user
to program the trace condition in the watchpoint monitor and to program a start or stop condition in the
trace buffer control register. The user can also program the TBCR with the conditions in which to stop
tracing: on an event, or when the buffer is full. TBCR0[IFSEL] specifies which interface transactions are
being captured.
The trace buffer can be programmed to trace the dispatch bus from any of the following:
Transactions come into the ECM, arbitrate for common resources, and get dispatched to the target port.
Information such as transaction types, source ID, and other attributes can be captured in any of the selected
interfaces.
21.4.5.1
Figure 21-20
when TBCR1[IFSEL] = 000.
Table 21-27
21-28
Reset
W
R
•
•
•
10–13
Bits
0–4
5–9
CMDTT CMDSID CMDTID CMDBC
e500 coherency module (ECM)
Outbound host interface to the PCI controller
Host interface to the DDR controller
0
Trace Buffer
describes the fields of CMD trace buffer entries.
4
CMDSID
CMDTID
Traced Data Formats (as a Function of TBCR1[IFSEL])
shows the trace buffer entry format for an ECM dispatch (CMD) transaction that is specified
CMDTT
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Name
Table 21-27. CMD Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 000)
5
Figure 21-20. e500 Coherency Module Dispatch (CMD) Trace Buffer Entry
9
Transaction type. Specifies the transaction type as shown in
of zero indicates a write with local processor snoop condition.
Source ID. Identifies the source of the transaction as shown in
value of 010101 indicates that DMA is the transaction source.
Target ID. Identifies the target of the transaction as shown in
of 010101 indicates that DMA is the transaction target.
10
13
14
18
19
—
31
All zeros
32
Function
Table
Table
CMDADDR
Table
21-12. For example, a value
21-26. For example, a value
21-26. For example, a
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