MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet
MPC8544COMEDEV
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MPC8544COMEDEV Summary of contents
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MPC8544E PowerQUICC™ III Integrated Host Processor Family Reference Manual Supports MPC8544E MPC8544 MPC8544ERM Rev. 1 10/2007 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...
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Reset, Clocking, and Initialization Part II—e500 Core Complex and L2 Cache Part III—Memory, Security, and I/O Interfaces Programmable Interrupt Controller Enhanced Three-Speed Ethernet Controllers Part IV—Global Functions and Debug Debug Features and Watchpoint Facility Complete List of Configuration, Control, and ...
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I Part I—Overview 1 Overview 2 Memory Map 3 Signal Descriptions 4 Reset, Clocking, and Initialization II Part II—e500 Core Complex and L2 Cache 5 Core Complex Overview 6 Core Register Summary 7 L2 Look-Aside Cache/SRAM III Part III—Memory, Security, ...
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... Application Examples.................................................................................................... 1-21 1.4.1 Multifunction Router Application ............................................................................. 1-22 1.4.2 Multifunction Printer Application ............................................................................. 1-23 1.4.3 Security Appliance..................................................................................................... 1-24 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Contents About This Book Part I Overview Chapter 1 Overview Page ...
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... Complete CCSR Map .................................................................................................... 2-14 3.1 Signals Overview ............................................................................................................. 3-1 3.2 Configuration Signals Sampled at Reset ....................................................................... 3-15 3.3 Output Signal States During Reset ................................................................................ 3-17 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Chapter 2 Memory Map Chapter 3 Signal Descriptions Page Number Freescale Semiconductor ...
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... Protocol ................................................................................................... 4-20 4.4.3.15 SGMII SerDes Reference Clock Configuration .................................................... 4-20 4.4.3.16 PCI Clock Selection............................................................................................... 4-21 4.4.3.17 PCI Speed Configuration ....................................................................................... 4-21 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 4 Reset, Clocking, and Initialization Page Number vii ...
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... MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)..................................... 5-25 5.9.3 Process ID Registers (PID0–PID2)............................................................................ 5-26 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 viii Contents Title Part II e500 Core Complex and L2 Cache Chapter 5 Core Complex Overview Page Number Freescale Semiconductor ...
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... Machine State Register (MSR) .................................................................................. 6-11 6.5.2 Processor ID Register (PIR) ...................................................................................... 6-13 6.5.3 Processor Version Register (PVR)............................................................................. 6-13 6.5.4 System Version Register (SVR)................................................................................. 6-14 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 6 Core Register Summary Page Number ix ...
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... MMU Control and Status Register 0 (MMUCSR0) .................................................. 6-32 6.12.3 MMU Configuration Register (MMUCFG) .............................................................. 6-32 6.12.4 TLB Configuration Registers (TLBnCFG)................................................................ 6-33 6.12.4.1 TLB0 Configuration Register 0 (TLB0CFG) ........................................................ 6-33 6.12.4.2 TLB1 Configuration Register 1 (TLB1CFG) ........................................................ 6-34 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... L2 Cache External Write Registers ....................................................................... 7-13 7.3.1.2.1 L2 Cache External Write Address Registers 0–3 (L2CEWARn) ...................... 7-13 7.3.1.2.2 L2 Cache External Write Address Registers Extended Address 0–3 (L2CEWAREAn)........................................................................................... 7-14 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 7 L2 Look-Aside Cache/SRAM Page Number ...
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... ECC Errors............................................................................................................. 7-34 7.9.3.2 Tag Parity Errors.................................................................................................... 7-34 7.9.4 L2 Cache States ......................................................................................................... 7-34 7.9.5 L2 State Transitions ................................................................................................... 7-35 7.9.6 Error Checking and Correcting (ECC) ...................................................................... 7-39 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xii Contents Title Page Number Freescale Semiconductor ...
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... Memory Interface Signals........................................................................................ 9-5 9.3.2.2 Clock Interface Signals............................................................................................ 9-9 9.3.2.3 Debug Signals.......................................................................................................... 9-9 9.4 Memory Map/Register Definition ................................................................................... 9-9 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Part III Memory, Security, and I/O Interfaces Chapter 8 e500 Coherency Module Chapter 9 ...
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... DDR SDRAM Interface Timing................................................................................ 9-54 9.5.4.1 Clock Distribution ................................................................................................. 9-57 9.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 9-58 9.5.6 DDR SDRAM Registered DIMM Mode ................................................................... 9-59 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xiv Contents Title Page Number Freescale Semiconductor ...
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... Block Revision Register 2 (BRR2)...................................................................... 10-19 10.3.1.3 Feature Reporting Register (FRR)....................................................................... 10-19 10.3.1.4 Global Configuration Register (GCR)................................................................. 10-20 10.3.1.5 Vendor Identification Register (VIR) .................................................................. 10-21 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 10 Programmable Interrupt Controller Page Number xv ...
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... Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3) ................. 10-43 10.3.7.6 Messaging Interrupt Destination Registers (MIDR0–MIDR3) ........................... 10-43 10.3.8 Per-CPU Registers ................................................................................................... 10-44 10.3.8.1 Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3).......................... 10-45 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xvi Contents Title Page Number Freescale Semiconductor ...
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... C Status Register (I2CSR) .................................................................................. 11-9 2 11.3.1 Data Register (I2CDR).................................................................................. 11-10 11.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR) ............................................11-11 11.4 Functional Description..................................................................................................11-11 11.4.1 Transaction Protocol .................................................................................................11-11 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter Interfaces Page Number xvii ...
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... Execution Units (EUs) ............................................................................................... 12-5 12.1.2.1 Public Key Execution Unit (PKEU) ...................................................................... 12-5 12.1.2.1.1 Elliptic Curve Operations .................................................................................. 12-5 12.1.2.1.2 Modular Exponentiation Operations ................................................................. 12-6 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xviii Contents Title Chapter 12 Security Engine (SEC) 2.1 Page Number Freescale Semiconductor ...
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... DEU Key Size Register (DEUKSR).................................................................... 12-34 12.4.2.3 DEU Data Size Register (DEUDSR)................................................................... 12-35 12.4.2.4 DEU Reset Control Register (DEURCR)............................................................ 12-35 12.4.2.5 DEU Status Register (DEUSR) ........................................................................... 12-36 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xix ...
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... RNG Mode Register (RNGMR).......................................................................... 12-63 12.4.5.2 RNG Data Size Register (RNGDSR) .................................................................. 12-63 12.4.5.3 RNG Reset Control Register (RNGRCR) ........................................................... 12-63 12.4.5.4 RNG Status Register (RNGSR)........................................................................... 12-64 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... KEU FIFOs .......................................................................................................... 12-90 12.5 Crypto-Channels .......................................................................................................... 12-91 12.5.1 Channel Registers .................................................................................................... 12-92 12.5.1.1 Crypto-Channel Configuration Registers 1–4 (CCCRn) ..................................... 12-92 12.5.1.2 Crypto-Channel Pointer Status Registers 1–4 (CCPSRn) ................................... 12-95 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxi ...
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... Detailed Signal Descriptions ..................................................................................... 13-3 13.3 Memory Map/Register Definition ................................................................................. 13-4 13.3.1 Register Descriptions................................................................................................. 13-6 13.3.1.1 Receiver Buffer Registers (URBR0, URBR1) (ULCR[DLAB .................... 13-6 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxii Contents Title Chapter 13 DUART Page Number Freescale Semiconductor ...
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... Modes of Operation ................................................................................................... 14-3 14.1.3.1 LBC Bus Clock and Clock Ratios ......................................................................... 14-3 14.1.3.2 Source ID Debug Mode ......................................................................................... 14-4 14.1.4 Power-Down Mode.................................................................................................... 14-4 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 14 Local Bus Controller Page Number xxiii ...
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... Chip-Select and Write Enable Negation Timing ............................................. 14-40 14.4.2.2.3 Relaxed Timing ............................................................................................... 14-41 14.4.2.2.4 Output Enable (LOE) Timing .......................................................................... 14-43 14.4.2.2.5 Extended Hold Time on Read Accesses .......................................................... 14-43 14.4.2.3 External Access Termination (LGTA) ................................................................. 14-46 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxiv Contents Title Page Number Freescale Semiconductor ...
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... Loop Control (LOOP) ..................................................................................... 14-69 14.4.4.4.6 Repeat Execution of Current RAM Word (REDO) ......................................... 14-69 14.4.4.4.7 Address Multiplexing (AMX) ......................................................................... 14-70 14.4.4.4.8 Data Valid and Data Sample Control (UTA) ................................................... 14-71 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxv ...
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... Host 60x Bus: HDI16 Peripheral Interface Hardware Timings..................... 14-101 14.5.6.2 Interfacing to MSC8102 DSI............................................................................. 14-102 14.5.6.2.1 DSI in Asynchronous SRAM-Like Mode ..................................................... 14-102 14.5.6.2.2 DSI in Synchronous Mode ............................................................................ 14-105 14.5.6.2.3 Broadcast Accesses.........................................................................................14-111 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxvi Contents Title Page Number Freescale Semiconductor ...
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... Receive Queue Control Register (RQUEUE) ................................................. 15-54 15.5.3.3.5 Receive Bit Field Extract Control Register (RBIFX)...................................... 15-56 15.5.3.3.6 Receive Queue Filer Table Address Register (RQFAR) ................................. 15-57 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 15 Page Number ...
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... Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K) ................. 15-82 15.5.3.6.6 Transmit and Receive 1024- to 1518-Byte Frame Counter (TRMAX)........... 15-83 15.5.3.6.7 Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter (TRMGV) .................................................................................................... 15-83 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxviii Contents Title Page Number Freescale Semiconductor ...
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... Carry Register 2 (CAR2) ............................................................................... 15-104 15.5.3.6.46 Carry Mask Register 1 (CAM1) .................................................................... 15-105 15.5.3.6.47 Carry Mask Register 2 (CAM2) .................................................................... 15-106 15.5.3.6.48 Receive Filer Rejected Packet Counter (RREJ) ............................................ 15-107 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxix ...
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... Reduced Gigabit Media-Independent Interface (RGMII) ................................. 15-129 15.6.1.5 Ten-Bit Interface (TBI)...................................................................................... 15-131 15.6.1.6 Reduced Ten-Bit Interface (RTBI) .................................................................... 15-132 15.6.1.7 Ethernet Physical Interfaces Signal Summary................................................... 15-133 15.6.2 Connecting to FIFO Interfaces .............................................................................. 15-137 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxx Contents Title Page Number Freescale Semiconductor ...
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... Setting Up the Receive Queue Filer Table .................................................... 15-165 15.6.5.1.6 Filer Example—802.1p Priority Filing.......................................................... 15-166 15.6.5.1.7 Filer Example—IP Diff-Serv Code Points Filing.......................................... 15-166 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxi ...
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... DMA Register Descriptions....................................................................................... 16-9 16.3.1.1 Mode Registers (MRn) ........................................................................................ 16-10 16.3.1.2 Status Registers (SRn) ......................................................................................... 16-12 16.3.1.3 Current Link Descriptor Address Registers (CLNDARn and ECLNDARn) ................................................................................................... 16-13 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxii Contents Title Chapter 16 DMA Controller Page Number Freescale Semiconductor ...
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... DMA Descriptors..................................................................................................... 16-34 16.4.5 Limitations and Restrictions .................................................................................... 16-37 16.5 DMA System Considerations ...................................................................................... 16-38 16.5.1 Unusual DMA Scenarios ......................................................................................... 16-40 16.5.1.1 DMA to e500 Core .............................................................................................. 16-40 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxiii ...
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... PCI Inbound Window Attributes Registers (PIWARn) ................................... 17-21 17.3.1.4 PCI Error Management Registers........................................................................ 17-23 17.3.1.4.1 PCI Error Detect Register (ERR_DR)............................................................. 17-24 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxiv Contents Title C ......................................................................................................... 16-40 Chapter 17 PCI Bus Interface Page Number Freescale Semiconductor ...
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... Power-Saving Modes and the PCI Arbiter .......................................................... 17-45 17.4.2 PCI Bus Protocol ..................................................................................................... 17-45 17.4.2.1 Basic Transfer Control......................................................................................... 17-45 17.4.2.2 PCI Bus Commands............................................................................................. 17-46 17.4.2.3 Addressing ........................................................................................................... 17-47 17.4.2.3.1 Memory Space Addressing.............................................................................. 17-47 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxv ...
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... Byte Order for Configuration Transactions ......................................................... 17-70 18.1 Introduction.................................................................................................................... 18-1 18.1.1 Overview.................................................................................................................... 18-1 18.1.1.1 Outbound Transactions .......................................................................................... 18-2 18.1.1.2 Inbound Transactions............................................................................................. 18-3 18.1.2 Features...................................................................................................................... 18-3 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxvi Contents Title Chapter 18 PCI Express Interface Controller Page Number Freescale Semiconductor ...
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... PCI Express Inbound Window Base Extended Address Registers (PEXIWBEARn) ......................................................................................... 18-27 18.3.5.2.6 PCI Express Inbound Window Attributes Registers (PEXIWARn) ................ 18-27 18.3.6 PCI Express Error Management Registers .............................................................. 18-29 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxvii ...
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... PCI Express Subordinate Bus Number Register—Offset 0x1A...................... 18-58 18.3.8.3.5 PCI Express Secondary Latency Timer Register—0x1B ................................ 18-59 18.3.8.3.6 PCI Express I/O Base Register—0x1C ........................................................... 18-59 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xxxviii Contents Title Page Number Freescale Semiconductor ...
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... PCI Express MSI Message Data Register (EP Mode Only)—0x7C ................... 18-80 18.3.10 PCI Express Extended Configuration Space ........................................................... 18-81 18.3.10.1 PCI Express Advanced Error Reporting Capability ID Register—0x100........... 18-82 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Page Number xxxix ...
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... Software INTx Message Generation ............................................................. 18-106 18.4.2.1.4 Software MSI Generation.............................................................................. 18-106 18.4.2.2 RC Handling of INTx Message and MSI Interrupt ........................................... 18-107 18.4.2.2.1 INTx Message Handling................................................................................ 18-107 18.4.2.2.2 MSI Handling ................................................................................................ 18-107 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Contents Title Page Number Freescale Semiconductor ...
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... Reset Request Status and Control Register (RSTRSCR) .................................... 19-18 19.4.1.16 Processor Version Register (PVR)....................................................................... 19-18 19.4.1.17 System Version Register (SVR)........................................................................... 19-19 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Part IV Global Functions and Debug Chapter 19 Global Utilities ...
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... Memory Map and Register Definition........................................................................... 20-3 20.3.1 Register Summary...................................................................................................... 20-3 20.3.2 Control Registers ....................................................................................................... 20-5 20.3.2.1 Performance Monitor Global Control Register (PMGC0) .................................... 20-5 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xlii Contents Title Chapter 20 Device Performance Monitor Page Number Freescale Semiconductor ...
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... Trace Buffer Control Registers (TBCR0, TBCR1) ............................................. 21-16 21.3.2.2 Trace Buffer Address Register (TBAR) .............................................................. 21-19 21.3.2.3 Trace Buffer Address Mask Register (TBAMR)................................................. 21-19 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Contents Title Chapter 21 Page Number xliii ...
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... Traced Data Formats (as a Function of TBCR1[IFSEL]).................................... 21-28 21.5 Initialization ................................................................................................................. 21-31 A.1 Changes From Revision 0 to Revision 1 ........................................................................ A-1 Complete List of Configuration, Control, and Status Registers MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xliv Contents Title Appendix A Revision History Appendix B Glossary Index Page Number Freescale Semiconductor ...
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... Three-Stage Load/Store Unit .................................................................................................. 5-8 5-5 Instruction Pipeline Flow ...................................................................................................... 5-14 5-6 GPR Issue Queue (GIQ) ....................................................................................................... 5-15 5-7 e500 Core Programming Model............................................................................................ 5-17 5-8 MMU Structure ..................................................................................................................... 5-23 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Figures Page Number xlv ...
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... L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 6-30 6-37 L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 6-31 6-38 Process ID Registers (PID0–PID2)....................................................................................... 6-32 6-39 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 6-32 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xlvi Figures Title Page Number Freescale Semiconductor ...
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... L2 Memory-Mapped SRAM Base Address Registers (L2SRBARn)................................... 7-16 7-12 L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1 (L2SRBAREAn) .............................................................................................................. 7-17 7-13 L2 Error Injection Mask High Register (L2ERRINJHI) ...................................................... 7-18 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number xlvii ...
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... DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 9-29 9-15 DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL).......................................................................... 9-30 9-16 DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-31 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xlviii Figures Title Page Number Freescale Semiconductor ...
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... Feature Reporting Register (FRR) ...................................................................................... 10-19 10-6 Global Configuration Register (GCR) ................................................................................ 10-20 10-7 Vendor Identification Register (VIR).................................................................................. 10-21 10-8 Processor Initialization Register (PIR) ............................................................................... 10-21 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number xlix ...
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... Processor Who Am I Register (WHOAMI)........................................................................ 10-47 10-46 Processor Interrupt Acknowledge Register (IACK) ........................................................... 10-47 10-47 End of Interrupt Register (EOI) .......................................................................................... 10-48 10-48 PIC Interrupt Processing Flow Diagram ............................................................................. 10- Block Diagram................................................................................................................ 11-1 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...
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... AFEU EU Go Register........................................................................................................ 12-49 12-29 MDEU Mode Register in Old Configuration (NEW = 0)................................................... 12-51 12-30 MDEU Mode Register in New Configuration (NEW = 1) ................................................. 12-52 12-31 MDEU Key Size Register ................................................................................................... 12-54 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number li ...
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... KEU Key Data Register_2 (CK-Low) ................................................................................ 12-90 12-70 KEU Key Data Register_3 (IK-high).................................................................................. 12-90 12-71 KEU Key Data Register_4 (IK-low)................................................................................... 12-90 12-72 Crypto-Channel Configuration Register (CCCR)............................................................... 12-92 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lii Figures Title Page Number Freescale Semiconductor ...
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... UPM Data Register (MDR) ................................................................................................ 14-20 14-10 SDRAM Machine Mode Register (LSDMR) ..................................................................... 14-21 14-11 UPM Refresh Timer (LURT) .............................................................................................. 14-23 14-12 LSRT SDRAM Refresh Timer (LSRT)............................................................................... 14-23 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number liii ...
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... SDRAM Two-Beat Burst Read, Page Closed 3........................................................ 14-55 14-45 SDRAM Four-Beat Burst Read, Page Miss 3........................................................... 14-55 14-46 SDRAM Single-Beat Write, Page Hit................................................................................. 14-56 14-47 SDRAM Three-Beat Write, Page Closed............................................................................ 14-56 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 liv Figures Title Page Number Freescale Semiconductor ...
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... Interface to MSC8102 DSI in Synchronous Mode ........................................................... 14-106 14-86 UPM Synchronization Cycle ............................................................................................ 14-107 14-87 Synchronous Single Write to MSC8102 DSI.................................................................... 14-108 14-88 Synchronous Single Read from MSC8102 DSI................................................................ 14-109 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lv ...
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... RBASE Register Definition ................................................................................................ 15-64 15-36 MACCFG1 Register Definition .......................................................................................... 15-67 15-37 MACCFG2 Register Definition .......................................................................................... 15-69 15-38 IPGIFG Register Definition ................................................................................................ 15-71 15-39 Half-Duplex Register Definition......................................................................................... 15-72 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lvi Figures Title Page Number Freescale Semiconductor ...
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... Transmit Multicast Packet Counter Register Definition ..................................................... 15-93 15-79 Transmit Broadcast Packet Counter Register Definition .................................................... 15-94 15-80 Transmit Pause Control Frame Counter Register Definition .............................................. 15-94 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lvii ...
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... TBI Control Register Definition ....................................................................................... 15-126 15-117 eTSEC-MII Connection .................................................................................................... 15-128 15-118 eTSEC-RMII Connection ................................................................................................. 15-129 15-119 eTSEC-RGMII Connection............................................................................................... 15-130 15-120 eTSEC-TBI Connection .................................................................................................... 15-131 15-121 eTSEC-RTBI Connection ................................................................................................. 15-132 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lviii Figures Title Page Number Freescale Semiconductor ...
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... Destination Stride Registers (DSRn) .................................................................................. 16-23 16-22 DMA General Status Register (DGSR) .............................................................................. 16-24 16-23 External Control Interface Timing ...................................................................................... 16-31 16-24 Stride Size and Stride Distance ........................................................................................... 16-33 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lix ...
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... PCI Configuration and Status Register Base Address Register (PCSRBAR) .................... 17-37 17-36 32-Bit Memory Base Address Register .............................................................................. 17-37 17-37 64-Bit Low Memory Base Address Register ...................................................................... 17-37 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev Figures Title Page Number Freescale Semiconductor ...
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... PCI Express PME and Message Interrupt Enable Register (PEX_PME_MES_IER) .................................................................................. 18-16 18-10 PCI Express Power Management Command Register (PEX_PMCR) ............................... 18-17 18-11 IP Block Revision Register 1 .............................................................................................. 18-18 18-12 IP Block Revision Register 2 .............................................................................................. 18-19 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxi ...
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... PCI Express Status Register................................................................................................ 18-46 18-41 PCI Express Revision ID Register ...................................................................................... 18-47 18-42 PCI Express Class Code Register ....................................................................................... 18-48 18-43 PCI Express Bus Cache Line Size Register ........................................................................ 18-48 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxii Figures Title Page Number Freescale Semiconductor ...
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... PCI Express Power Management Status and Control Register........................................... 18-69 18-82 PCI Express Power Management Data Register................................................................. 18-69 18-83 PCI Express Capability ID Register.................................................................................... 18-70 18-84 PCI Express Capabilities Register ...................................................................................... 18-70 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxiii ...
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... PCI Express PCI Interrupt Mask Register (PEX_SS_INTR_MASK)................................ 18-96 18-122 Requestor/Completer Relationship ..................................................................................... 18-97 18-123 PCI Express High-Level Layering ...................................................................................... 18-97 18-124 PCI Express Packet Flow.................................................................................................... 18-98 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxiv Figures Title Page Number Freescale Semiconductor ...
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... Performance Monitor Local Control Register B0 (PMLCB0).............................................. 20-8 20-6 Performance Monitor Local Control Register B (PMLCB1–PMLCB9) .............................. 20-9 20-7 Performance Monitor Counter Register 0 (PMC0)............................................................. 20-10 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figures Title Page Number lxv ...
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... Coherency Module Dispatch (CMD) Trace Buffer Entry .......................................... 21-28 21-21 DDR Trace Buffer Entry ..................................................................................................... 21-29 21-22 PCI Trace Buffer Entry ....................................................................................................... 21-29 21-23 PCI Express Trace Buffer Entry.......................................................................................... 21-30 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxvi Figures Title Page Number Freescale Semiconductor ...
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... Serial Configuration ............................................................................................... 4-18 4-19 eTSEC3 Serial Configuration ............................................................................................... 4-18 4-20 eTSEC1/eTSEC2 Width Configuration ................................................................................ 4-19 4-21 eTSEC3/eTSEC4 Width Configuration ................................................................................ 4-19 4-22 eTSEC1 Protocol Configuration ........................................................................................... 4-20 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Tables Page Number lxvii ...
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... HID1 Field Descriptions ....................................................................................................... 6-26 6-20 L1CSR0 Field Descriptions .................................................................................................. 6-28 6-21 L1CSR1 Field Descriptions .................................................................................................. 6-29 6-22 L1CFG0 Field Descriptions .................................................................................................. 6-30 6-23 L1CFG1 Field Descriptions .................................................................................................. 6-31 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxviii Tables Title Page Number Freescale Semiconductor ...
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... L2CAPTDATALO Field Description.................................................................................... 7-20 7-15 L2CAPTECC Field Descriptions .......................................................................................... 7-21 7-16 L2ERRDET Field Descriptions ............................................................................................ 7-21 7-17 L2ERRDIS Field Descriptions.............................................................................................. 7-22 7-18 L2ERRINTEN Field Descriptions ........................................................................................ 7-23 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxix ...
Page 70
... DDR_SDRAM_MODE_2 Field Descriptions...................................................................... 9-26 9-16 DDR_SDRAM_MD_CNTL Field Descriptions................................................................... 9-27 9-17 Settings of DDR_SDRAM_MD_CNTL Fields .................................................................... 9-28 9-18 DDR_SDRAM_INTERVAL Field Descriptions .................................................................. 9-29 9-19 DDR_DATA_INIT Field Descriptions ................................................................................. 9-29 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxx Tables Title Page Number Freescale Semiconductor ...
Page 71
... Processor Interrupts Generated Outside the Core—Types and Sources ............................... 10-3 10-2 e500 Core-Generated Interrupts that Cause a Wake-Up ....................................................... 10-4 10-3 Internal Interrupt Sources...................................................................................................... 10-6 10-4 PIC Interface Signals ............................................................................................................ 10-7 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxi ...
Page 72
... EIDRn Field Descriptions................................................................................................... 10-40 10-42 IIVPRn Field Descriptions.................................................................................................. 10-41 10-43 IIDRn Field Descriptions .................................................................................................... 10-42 10-44 MIVPRn Field Descriptions................................................................................................ 10-43 10-45 MIDRn Field Descriptions.................................................................................................. 10-44 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxii Tables Title Page Number Freescale Semiconductor ...
Page 73
... AFEU Reset Control Register Field Descriptions .............................................................. 12-45 12-23 AFEU Status Register Field Descriptions........................................................................... 12-46 12-24 AFEU Interrupt Status Register Field Descriptions............................................................ 12-47 12-25 AFEU Interrupt Control Register Field Descriptions ......................................................... 12-48 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxiii ...
Page 74
... Master Control Register (MCR) Field Descriptions ......................................................... 12-114 13-1 DUART Signal Overview ..................................................................................................... 13-3 13-2 DUART Signals—Detailed Signal Descriptions .................................................................. 13-3 13-3 DUART Register Summary .................................................................................................. 13-5 13-4 URBR Field Descriptions ..................................................................................................... 13-6 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxiv Tables Title Page Number Freescale Semiconductor ...
Page 75
... LTEDR Field Descriptions.................................................................................................. 14-26 14-18 LTEIR Field Descriptions ................................................................................................... 14-27 14-19 LTEATR Field Descriptions................................................................................................ 14-28 14-20 LTEAR Field Descriptions.................................................................................................. 14-29 14-21 LBCR Field Descriptions.................................................................................................... 14-29 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxv ...
Page 76
... DMACTRL Field Descriptions........................................................................................... 15-35 15-14 TBIPA Field Descriptions ................................................................................................... 15-37 15-15 TCTRL Field Descriptions.................................................................................................. 15-37 15-16 TSTAT Field Descriptions................................................................................................... 15-40 15-17 DFVLAN Field Descriptions .............................................................................................. 15-43 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxvi Tables Title Page Number Freescale Semiconductor ...
Page 77
... MAC01ADDR2–MAC15ADDR2 Field Descriptions ....................................................... 15-80 15-55 TR64 Field Descriptions ..................................................................................................... 15-81 15-56 TR127 Field Descriptions ................................................................................................... 15-81 15-57 TR255 Field Descriptions ................................................................................................... 15-81 15-58 TR511 Field Descriptions ................................................................................................... 15-82 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxvii ...
Page 78
... TOVR Field Descriptions ................................................................................................. 15-100 15-96 TUND Field Descriptions ................................................................................................. 15-101 15-97 TFRG Field Descriptions .................................................................................................. 15-101 15-98 CAR1 Field Descriptions .................................................................................................. 15-103 15-99 CAR2 Field Descriptions .................................................................................................. 15-104 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxviii Tables Title Page Number Freescale Semiconductor ...
Page 79
... Interrupt Coalescing Timing Threshold Ranges ............................................................... 15-154 15-137 Transmission Errors .......................................................................................................... 15-155 15-138 Reception Errors ............................................................................................................... 15-156 15-139 Tx Frame Control Block Descriptions .............................................................................. 15-159 15-140 Rx Frame Control Block Descriptions.............................................................................. 15-161 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxix ...
Page 80
... CLNDARn Field Descriptions............................................................................................ 16-15 16-9 SATRn Field Descriptions .................................................................................................. 16-16 16-10 SARn Field Descriptions .................................................................................................... 16-17 16-11 DATRn Field Descriptions.................................................................................................. 16-18 16-12 DARn Field Descriptions.................................................................................................... 16-19 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxx Tables Title Page Number Freescale Semiconductor ...
Page 81
... PCI Revision ID Register Field Descriptions ..................................................................... 17-34 17-29 PCI Bus Programming Interface Register Field Description.............................................. 17-34 17-30 PCI Subclass Code Register Field Description................................................................... 17-35 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxi ...
Page 82
... PCI Express IP Block Revision Register 2 Field Descriptions........................................... 18-19 18-15 PEXOTARn Field Descriptions .......................................................................................... 18-20 18-16 PCI Express Outbound Extended Address Translation Register n Field Descriptions ......................................................................................... 18-21 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxii Tables Title Page Number Freescale Semiconductor ...
Page 83
... Low Memory Base Address Register Field Descriptions........................................ 18-52 18-47 Bit Setting for 64-Bit High Memory Base Address Register.............................................. 18-52 18-48 PCI Express Subsystem Vendor ID Register Field Description ......................................... 18-53 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxiii ...
Page 84
... PCI Express Slot Control Register Field Description ......................................................... 18-76 18-88 PCI Express Slot Status Register Field Descriptions.......................................................... 18-76 18-89 PCI Express Root Control Register Field Description........................................................ 18-77 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxiv Tables Title Page Number Freescale Semiconductor ...
Page 85
... External Signal Summary ..................................................................................................... 19-2 19-2 Detailed Signal Descriptions................................................................................................. 19-2 19-3 Global Utilities Block Register Summary ............................................................................ 19-3 19-4 PORPLLSR Field Descriptions ............................................................................................ 19-5 19-5 PORBMSR Field Descriptions ............................................................................................. 19-6 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxv ...
Page 86
... Register Settings for Counting Examples ........................................................................... 20-28 21-1 POR Configuration Settings and Debug Modes ................................................................... 21-3 21-2 Debug, Watchpoint and Test Signal Summary...................................................................... 21-5 21-3 Debug Signals—Detailed Signal Descriptions ..................................................................... 21-7 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxvi Tables Title Page Number Freescale Semiconductor ...
Page 87
... PCI Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 010) ................................................................................................. 21-30 21-30 PCI Express Trace Buffer Entry Field Descriptions (TBCR1[IFSEL] = 100 or 101 or 110)........................................................................... 21-30 B-1 Memory Map...........................................................................................................................B-1 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Tables Title Page Number lxxxvii ...
Page 88
... Table Number MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 lxxxviii Tables Title Page Number Freescale Semiconductor ...
Page 89
... Chapter 6, “Core Register Summary,” MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor provides a high-level description of features and functionality of the describes the device memory map. An overview of the local address lists all the external signals, cross-references for signals that ...
Page 90
... I 2.1,” describes the security controller of the MPC8544E. describes the (dual) universal asynchronous receiver/transmitters describes the local bus controller of the MPC8544E. The main 2 C) bus controllers of the MPC8544E controller to initialize describes the two enhanced Freescale Semiconductor ...
Page 91
... The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, by International Business Machines, Inc. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor describes the four-channel general-purpose DMA controller of the describes the PCI controller of the MPC8544E. Controller,” describes the PCI-Express implementation of the defines the global utilities of the MPC8544E ...
Page 92
... Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale processors. Additional literature is published as new processors become available. For a current list of documentation, refer to http://www.freescale.com. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xcii describes the functionality of the e500 Freescale Semiconductor ...
Page 93
... Indicates a read-only bit field in a memory-mapped register. R FIELDNAME W Indicates a write-only bit field in a memory-mapped register. Although these bits R can be written to as ones or zeros, they are always read as zeros. W FIELDNAME MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor xciii ...
Page 94
... Enhanced host port interface EPROM Erasable programmable read-only memory FCS Frame-check sequence GCI General circuit interface MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xciv Section 3.2, “Configuration Signals Sampled at Reset.” Table i. Acronyms and Abbreviated Terms Meaning Freescale Semiconductor ...
Page 95
... Nonmultiplexed serial interface No-op No operation OCeaN On-chip network OSI Open systems interconnection PCI Peripheral component interconnect bus PCMCIA Personal Computer Memory Card International Association PCS Physical coding sublayer MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Meaning xcv ...
Page 96
... Time-slot assigner TSEC Three-speed Ethernet controller Tx Transmit TxBD Transmit buffer descriptor UART Universal asynchronous receiver/transmitter UPM User-programmable machine UTP Unshielded twisted pair VA Virtual address ZBT Zero bus turnaround MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 xcvi Meaning Freescale Semiconductor ...
Page 97
... Chapter 4, “Reset, Clocking, and Initialization,” sequence, power-on reset (POR) configuration, clocking, and initialization of the MPC8544E. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor provides a listing of all the external signals, cross-references for signals describes the hard and soft resets, power-on reset ...
Page 98
... Overview MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 I-2 Freescale Semiconductor ...
Page 99
... The MPC8544E is also available without a security engine configuration known as the MPC8544. All specifications other than those relating to security apply to the MPC8544 exactly as described in this document. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 2 C controllers, a four-channel 1-1 ...
Page 100
... Figure 1-1. MPC8544E Block Diagram Figure 1-1 shows the major functional SRAM e500 Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Bus Cache Cache PCI Express dual x4 and Interfaces single x1 PCI 32-bit 32-bit PCI Bus Interface 66 MHz 4-Channel DMA External Control Controller Freescale Semiconductor ...
Page 101
... Contiguous or discontiguous memory mapping — Chip-select interleaving support — Sleep mode support for self-refresh SDRAM MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor includes a comprehensive list of e500 core features. Section 1.3.2, “On-Chip Memory Unit” Overview ...
Page 102
... Implements the Rijndael symmetric key cipher – ECB, CBC, CTR, and CCM modes – 128-, 192-, and 256-bit key lengths MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-4 m and F(p) modes and programmable field size Freescale Semiconductor ...
Page 103
... Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8, 16 bits) MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 2 C addressing mode Overview 2 ...
Page 104
... VRRP and HSRP support for seamless router fail-over – exact-match MAC addresses supported – Broadcast address (accept/reject) – Hash table match 512 multicast addresses MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-6 Section 1.3.13, for more information. Freescale Semiconductor ...
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... Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency • PCI Express interfaces — PCI Express 1.0a compatible — Supports dual x4 and single x1 links MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-7 ...
Page 106
... This device uses the e500 microprocessor core complex. The e500 core has an internal PLL that allows independent optimization of the operating frequencies. The core frequencies are derived from either the MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-8 Freescale Semiconductor ...
Page 107
... Pseudo-LRU replacement algorithm — Copy-back data cache • Dual-dispatch superscalar • Precise exception handling MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE NOTE Overview 1-9 ...
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... Book E instructions also executes the lower half of 64-bit SPE APU instructions. — Single-cycle integer add and subtract — Single-cycle logical operations — Single-cycle shift and rotate MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-10 Freescale Semiconductor ...
Page 109
... Floating-point data exception – Floating-point round exception – Performance monitor • Memory management unit (MMU) — Data L1 MMU – Four-entry, fully-associative TLB array for variable-sized pages MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-11 ...
Page 110
... Stashing of I/O data into the L2 array is supported, but can be limited to a 1-, 2-, or 4-way basis — SRAM operation is byte-accessible. — Data ECC on 64-bit boundaries (single-error correction, double-error detection) MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev virtual memory physical memory Freescale Semiconductor ...
Page 111
... I/O writes that correspond to a programmable address window or that use a special transaction type (stashing). In this way, DMA engines or I/O devices can force data into the cache. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-13 ...
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... MPC8544E interrupt controller to the IRQ_OUT signal. The IRQ_OUT signal from the interrupt controller is steered to an enable bit in the DDR controller which immediately causes main memory to enter self-refresh mode. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-14 Freescale Semiconductor ...
Page 113
... The version of the SEC used in the MPC8544E is specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE Overview 1-15 ...
Page 114
... C) interfaces. The controller consists of a transmitter/receiver 2 C units support general broadcast mode, and on-chip Figure 1-2. The bus FIFO FIFO FIFO AESU AFEU KEU RNG FIFO FIFO FIFO FIFO 2 C bus is a two-wire, bidirectional 2 C devices such allows the Freescale Semiconductor ...
Page 115
... JEDEC–compliant SDRAM devices. An internal PLL (phase-locked loop) for bus clock generation ensures improved data setup margins for board designs. The SDRAM MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 2 C interface to access an external serial ROM ...
Page 116
... Bare IP packets, with an optional 32-bit CRC check sequence, can be transferred to the eTSEC directly. The eTSEC Tx and Rx FIFOs, TCP/IP acceleration functions, and DMA continue to be used in packet FIFO mode. There are no mode configuration dependencies between eTSEC1 and eTSEC3. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-18 Freescale Semiconductor ...
Page 117
... The interface is selectable at boot time to support either 32 or 64-bit addressing. The maximum supported packet payload size is 256 bytes. The physical layer supports dual x4 links and a single x1 link. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Overview 1-19 ...
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... The local address map is 64 Gbytes. The MPC8544E can be made part of a larger system address space through the mapping of translation windows. This functionality is included in the address translation and mapping units (ATMUs). Both inbound and outbound translation MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-20 Freescale Semiconductor ...
Page 119
... ECM are coherent transactions; all others (across the on-chip fabric) are non-coherent. 1.4 Application Examples The MPC8544E is a very flexible device and can be configured to meet many system application needs. The following section provides block diagrams of various applications. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figure 1-3 Overview ...
Page 120
... Figure 1-4. Multi-function Router Application Enabled by local bus, PCI Express, MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-22 DDR/DDR-2 Flash SDRAM Local Bus DDR MPC8544E S/RGMII SEC PCIe ASIC/FPGA PCI, and Ethernet RGMII 5/9 Port GE Switch w/PHY 10/100/1000 Ethernet Network Interface Freescale Semiconductor ...
Page 121
... USB2.0 SATA S/RGMII 10/100/1000 Ethernet Network Interface Maintenance/Debug Port Figure 1-5. Multifunction Printer Application Enabled by Local Bus, PCI Express, MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor DDR/DDR-2 Flash SDRAM Local Bus DDR MPC8544E PCIe 10/100/1000 Expansion ...
Page 122
... Figure 1-6. Security Appliance Enabled by SEC, local bus, PCI, and Ethernet MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-24 DDR/DDR-2 Flash Flash SDRAM Local Bus MPC8544E SEC PCI/PCIe System Interface DDR S/RGMII 10/100/1000 Ethernet Protected Connection Freescale Semiconductor ...
Page 123
... MPC8544E SAN host adapter enabled by local bus, PCI Express, and Ethernet. Local Bus SATA II PCIe PCIe RAID Controller Figure 1-7. IP SAN Host Adapter enabled by local bus, PCI Express, and Ethernet MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor DDR/DDR-2 SDRAM Flash DDR S/RGMII MPC8544E S/RGMII XOR ...
Page 124
... TDM MSC81xx2 DSP Figure 1-8. VoIP Aggregation Application Enabled by local bus and Ethernet MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 1-26 Compact DDR/DDR-2 Flash Flash SDRAM Local Bus R/GMII MPC8544E DDR S/RGMII 10/100/1000 Ethernet Backplane/Network Interfaces Freescale Semiconductor ...
Page 125
... PCI Express 1 PCI Express 3 Local bus DDR SDRAM 1 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 2-1. Target Interface Codes Target Interface The general intent of the Target Interface Codes is to maintain consistency across PowerQUICC III family devices. ...
Page 126
... Table 2-2. Local Access Windows Example Base Address Size 0x0_0000_0000 2 Gbytes 0x0_8000_0000 1 Mbyte 0x0_A000_0000 256 Mbytes 0x0_C000_0000 256 Mbytes 0x8_0000_0000 32 Gbytes Unused 0x0_A000_0000 PCI 0x0_B000_0000 0x0_C000_0000 Local Bus Target Interface 0b1111 (DDR SDRAM) 0b0100 (local bus) 0b0000 (PCI) 0b0100 (local bus) 0b0100 (PCI Express) Freescale Semiconductor ...
Page 127
... High-order address bits defining location of the window in the initial address space Window size/attributes Window enable, window size, target interface, and transaction attributes MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Location”). However, note that the e500 core only Table 2-3 Function ...
Page 128
... The local access window registers exist as part of the local access block in the general utilities registers. See Section 2.3.4, “General Utilities Registers.” MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-4 Section 2.1, “Local Memory Map Overview and A detailed description of the local access window for and Freescale Semiconductor ...
Page 129
... LAWAR8—Local access window 8 attribute register 0x0_0D28 LAWBAR9—Local access window 9 base address register 0x0_0D30 LAWAR9—Local access window 9 attribute register MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Register Memory Map Access Reset Section/Page R 0x0000_0000 2 ...
Page 130
... MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-6 Figure 15 16 All zeros Table 2-5. LAIPBRR1 Field Descriptions Description Figure IP_INT All zeros Table 2-6. LAIPBRR2 Field Descriptions Description 2-2. Access: Read only 23 24 IP_MJ IP_MN 2-3. Access: Read only 23 24 IP_CFG Freescale Semiconductor 31 31 ...
Page 131
... The local access window n is enabled and other LAWAR n and LAWBAR n fields combine to identify an address range for this window. 1–7 — Write reserved, read = 0 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 8 BASE_ADDR All zeros Table 2-7. LAWBAR n Field Descriptions Description ...
Page 132
... MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-8 Description bytes Table 2-9, local access window 1 governs the mapping of the 1-Mbyte Size 1 Mbyte 0b0100 (Local bus controller —LBC) 2 Gbytes 0b1111 (DDR SDRAM) (SIZE+1) bytes. Target Interface Freescale Semiconductor ...
Page 133
... Inbound address translation and mapping refers to the translation of an address from the external address space of an I/O interface (such as PCI address space) to the local 36-bit address space understood by the MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Section 18.3.5.1, “PCI Express Outbound ATMU Registers” Memory Map ...
Page 134
... When the local e500 processor is used to configure CCSR space, the CCSR memory space should typically be marked as cache-inhibited and guarded. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-10 for a detailed description of the PCI Express inbound ATMU NOTE Section 17.3.1.3, “PCI ATMU Section 18.3.5.1, “PCI Section 4.3.1.1.2, The default value for Freescale Semiconductor ...
Page 135
... Table 2-10. Local Memory Configuration, Control, and Status Register Summary Offset from CCSRBAR 0x0_0000–0x3_FFFF 0x4_0000–0x7_FFFF 0x8_0000–0xB_FFFF 0xC_0000–0xD_FFFF 0xE_0000–0xF_FFFF MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Register Grouping General utilities Programmable interrupt controller (PIC) Reserved Reserved Device-specific utilities Memory Map Section 17.3.2.11, “ ...
Page 136
... DMA 0x2 4000 eTSEC 1 0x2 5000 0x2 6000 eTSEC 3 0x2 7000 0x3 0000 SEC 0x3 FFFF and Status Memory Block General Utility Block 0xn n000 General Registers 0xn nC00 ATMU 0xn nE00 Error Mgmt 0xn nF00 Debug Freescale Semiconductor ...
Page 137
... Also, when reading from a register, software should not rely on the value of any reserved bit remaining consistent. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE PIC Registers ...
Page 138
... PowerQUICC III TSECs. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-14 0xE 0000 0xE 1000 0xE 2000 0xF FFFC and Status Memory Block NOTE Device-Specific Registers Global Utilities Perf. Monitor Watchpoint/Debug Freescale Semiconductor ...
Page 139
... Reserved 0x2_6000 eTSEC3 0x2_7000– Reserved 0x3_0FFF MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 2-11. CCSR Block Base Address Map Block Section/Page General Utilities (0x0_0000–0x3_FFFF) 17.3/17-11 15.5/15-13 15.5/15-13 Comments 4.3.1/4-4 0x0_0000: Configuration, control, ...
Page 140
... Watchpoint Monitor and Trace Buffer 0xE_3000– Reserved 0xF_FFFF MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 2-16 Block Section/Page 12.2/12-10 10.3.1/10-18 10.3.7/10-39 10.3.8/10-44 Reserved (0x8_0000–0xD_FFFF) Device Specific Utilities (0xE_0000–0xF_FFFF) 19.4/19-3 20.3/20-3 21.3/21-10 Comments Freescale Semiconductor ...
Page 141
... Note that these figures show multiplexed signals multiple times. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE illustrate the external signals of the MPC8544E, showing how the ...
Page 142
... LSSD_MODE L1_TSTCLK L2_TSTCLK TEST_SEL TEMP_ANODE, TEMP_CATHODE TCK TDI TDO TMS TRST SD1_TX[7:0], SD1_TX[7:0] SD1_RX[7:0], SD1_RX[7:0] SD1_REF_CLK, SD1_REF_CLK SD2_TX[3:0], SD2_TX[3:0] SD2_RX[3:0], SD2_RX[3:0] SD2_REF_CLK, SD2_REF_CLK UART_SIN[0:1] UART_SOUT[0:1] UART_CTS[0:1] UART_RTS[0:1] Freescale Semiconductor Gen. Purpose Clock Test JTAG SerDes Interface 1 SerDes Interface 2 Dual UART Interface ...
Page 143
... EC_GTX_CLK125 Ethernet PIC IRQ9/DMA_DREQ3 Interface IRQ10/DMA_DACK3 IRQ11/DMA_DDONE3 UART_SOUT[0:1] Dual UART UART_CTS[0:1] Interface UART_RTS[0:1] Figure 3-2. MPC8544E Signal Groupings (2/3) (Continued) MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 1 1 EC_MDC 1 EC_MDIO MCP 1 1 UDE 1 1 IRQ[0: IRQ_OUT ...
Page 144
... LDP[0:3] cfg_cpu_boot/LA[27 cfg_sys_pll[0:3]/LA[28:31 cfg_sec_freq/LWE0/LBS0 3 LCS[0:4] 5 cfg_host_agt[0:2]/LWE[1:3]/LBS[1: cfg_core_pll[0]/LBCTL 1 1 cfg_core_pll[1]/LALE 1 1 cfg_core_pll[2]/LGPL2/LOE/LSDRAS cfg_dram_type[0]/LGPL0/LSDA10 1 1 cfg_dram_type[1]/LGPL1/LSDWE 1 1 cfg_boot_seq[0]/LGPL3/LSDCAS 1 1 cfg_boot_seq[1]/LGPL5 cfg_mem_debug/MSRCID[ cfg_ddr_debug/MSRCID[ LCKE 1 LCLK[0: Configuration Freescale Semiconductor ...
Page 145
... PCI initiator ready PCI_STOP PCI stop PCI_DEVSEL PCI device select PCI_IDSEL PCI initial device select MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 3-1 lists signals grouped by function, Functional Alternate Function(s) Block DDR memory — DDR memory — ...
Page 146
... I/O Signals Page 1 I/O 17-2/17-6 1 I/O 17-2/17-6 1 I/O 17-2/17 17-2/17-6 1 I/O 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17 17-2/17-6 1 I/O 17-2/17 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15-9 1 I/O 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15-9 Freescale Semiconductor ...
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... LGPL0 Local bus UPM general purpose line 0 LGPL1 Local bus GP line 1 LGPL2 Local bus GP line 2 /LOE /output enable MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block eTSEC3 FIFO3_TXD[6:4] /cfg_io_ports[0:2] eTSEC3 FIFO3_TXD3 eTSEC3 FIFO3_TXD2 ...
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... Signals Page 1 O 14-2/14-5 1 I/O 14-2/14 14-2/14 14-2/14 14-2/14 14-2/14 14-2/14 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 10-5/10 10-5/10 10-5/10 10-5/10 10-5/10 10-5/10 10-5/10 13-2/13 13-2/13 13-2/13 13-2/13-3 1 I/O 11-2/11-4 1 I/O 11-2/11-4 1 I/O 11-2/11-4 1 I/O 11-2/11 Freescale Semiconductor ...
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... Memory debug source port ID 2–4 MDVAL Memory debug data valid LSSD_MODE LSSD mode L1_TSTCLK L1 test clock MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block PCI Express 2 — PCI Express 1 — PCI Express 2 — ...
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... Page 1 I 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 4-3/4 4-3/4 19-2/19-2 No. of Table/ I/O Signals Page 1 O 19-2/19 19-2/19 19-2/19 19-2/19 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 16-3/16 17-2/17 17-2/17-6 1 I/O 17-2/17 19-2/19-2 19.4.1.9/19-12 Freescale Semiconductor ...
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... LGPL3 Local bus GP line 3 LGPL4 Local bus GP line 4 /LGTA/ /GPCM terminate access LUPWAIT /UPM wait MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block General- — purpose outputs System control — System control — ...
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... Page 1 O 14-2/14 21-5/21 14-2/14 14-2/14 14-2/14 14-2/14 9-3/9 9-3/9 9-3/9 9-3/9 9-3/9 10-5/10 9-3/9 9-3/9 9-3/9-5 64 I/O 9-3/9-5 8 I/O 9-3/9-5 9 I/O 9-3/9-5 1 I/O 9-3/9 21-3/21-7 8 I/O 9-3/9 9-3/9 21-3/21 21-3/21 21-3/21 9-3/9-5 32 I/O 17-2/17-6 4 I/O 17-2/17 17-2/17-6 Freescale Semiconductor ...
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... SD2_RX[0] receive data complement SD2_RX[3:2], Receive data, SD2_RX[3:2] receive data complement SD2_TX[0], Transmit data, SD2_TX[0] transmit data complement MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) Block PCI — PCI — PCI — PCI ...
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... FIFO3_RX_FC No. of Table/ I/O Signals Page 4-2/4 4-3/4 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-5/21 21-4/21 21-4/21 21-5/21 15-2/15-9 1 I/O 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15 15-2/15-9 1 I/O 15-2/15-9 Freescale Semiconductor ...
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... Most of the reset configuration signals have internal pull-up resistors so that if the signals are not driven, the default value is high (a one), as shown in the table. Some signals do not have MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Functional Alternate Function(s) ...
Page 156
... Indeterminate if not driven (no default) cfg_cpu_boot 1 cfg_sys_pll[0:3] Must be driven cfg_host_agt[0:2] 111 cfg_core_pll[0] Must be driven cfg_core_pll[1] Must be driven cfg_core_pll[2] Must be driven cfg_dram_type[0] 1 cfg_dram_type[1] 1 cfg_boot_seq[0] 1 cfg_boot_seq[1] 1 cfg_mem_debug 1 cfg_ddr_debug 1 Freescale Semiconductor ...
Page 157
... TSEC3 TSEC3 TSEC3 TSEC3 TSEC3 LBC LBC LBC LBC DMA DMA MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor for a complete description of the reset functionality. Signal MBA[2:0] MA[15:0] MWE MRAS MCAS MCS[0:3] MCKE[0:3] MCK[0:5], MCK[0:5] MODT[0:3] SD_TX[7:0], SD_TX[7:0] ...
Page 158
... Input—reset config (test only) MDVAL ASLEEP Input—reset config (test only) CLK_OUT GPOUT[0:7] TDO Section 4.4.3.9, “DDR SDRAM Type,” on page 4-18 State During Reset High-Z 2 Driven (test only) High-Z High-Z High-Z 2 High High-Z 2 Driven Toggling High-Z Driven Freescale Semiconductor ...
Page 159
... Second SERDES high-speed interface reference clock SD2_REF_CLK The following sections describe the reset and clock signals in detail. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor contains references to additional sections that contain more information. Table 4-1. Signal Summary Description ...
Page 160
... TOSR[SEL] equals 0b000. See Section 4.4.2, “Power-On Reset Sequence,” Subsequent assertion/negation due to power down modes occurs asynchronously. Section 4.4.3, “Power-On Reset and Section 4.4.3, “Power-On Section 11.4.5, “Boot Chapter 21, “Debug Features and Watchpoint for more information. Freescale Semiconductor ...
Page 161
... Timing Assertion/Negation—See the MPC8544E Integrated Processor Hardware Specifications for specific timing information for this signal. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Reset, Clocking, and Initialization Description Section 4.4.4.4, “Real Time Clock.” ...
Page 162
... The effect of the update must be guaranteed to be visible by the MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-4 Register Access Reset Section/Page R/W 0x000F_F700 4.3.1.1.2/4-5 R/W 0x0000_0000 4.3.1.2.1/4-6 R/W 0x0000_0000 4.3.1.2.1/4-6 R/W 0x0000_0000 4.3.1.3.1/4-7 Freescale Semiconductor ...
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... BASE_ADDR Identifies the16 most-significant address bits of the window used for configuration accesses. The base address is aligned on a 1-Mbyte boundary. 24–31 — Write reserved, read = 0 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 7 8 BASE_ADDR 1 Table 4-5. CCSRBAR Bit Settings ...
Page 164
... Figure 4-3. Alternate Configuration Attribute Register (ALTCAR) MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-6 for more information. NOTE 7 8 BASE_ADDR All zeros Table 4-6. ALTCBAR Bit Settings Description TRGT_ID All zeros Access: Read/Write — Access: Read/Write 31 — Freescale Semiconductor ...
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... R EN — W Reset Figure 4-4. Boot Page Translation Register (BPTR) MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-7. ALTCAR Bit Settings Description 1001–1010 Reserved 1011 Security 1100 Reserved 1101 Reserved 1110 Reserved 1111 Local memory —DDR SDRAM and on-chip Section 4.4.3.4, “ ...
Page 166
... Section 4.4.3.8, “Boot Sequencer Configuration.” Section 11.4.5, “Boot Sequencer Mode,” for more information on the setting of the soft reset flag. Note that interface and writes data to The boot sequencer the I C chapter. Section 19.4.1.14, “Machine Check Section 4.4.2, Freescale Semiconductor If the ...
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... When PLL locking is completed, the boot sequencer is released, causing it to load configuration data from serial ROMs, if enabled, as described in Configuration.” MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Mode,” and Section 11.4.5.2, “EEPROM Data Section 19.4.1.18, “Reset Control Register NOTE: Section 4.4.3.8, “ ...
Page 168
... MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-10 Section 4.4.3.7, “CPU Boot Configuration.” Section 21.3.4.1, “Trigger Out Source Register (TOSR),” Section 21.3.4, “Trigger Out Function.” Section 19.4.1, “Register Descriptions.” Figure 4-5. Power-On Reset Sequence The for more For more Freescale Semiconductor ...
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... Note that the values latched on these signals during POR are accessible in the PORPLLSR (POR PLL status register), as described in (PORPLLSR).” MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE Table 4-9, establish the clock ratio between the SYSCLK input and the Section 19.4.1.1, “ ...
Page 170
... HID1 register, as Table 4-10. e500 Core Clock PLL Ratios Reset Configuration Name Value (Binary) cfg_core_pll[0:2] CCB Clock : SYSCLK Ratio Reserved Reserved Reserved Reserved Reserved Reserved Reserved e500 Core: CCB ClockRatio 000 001 Reserved 010 011 (1 100 101 (2.5:1) 110 111 (3 Freescale Semiconductor ...
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... Note that the values latched on these signals during POR are accessible through the memory-mapped PORBMSR (POR boot mode status register) described in Register (PORBMSR).” MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-11, is used to establish the ratio of the e500 Core Table 4-11. SEC Mode Configuration ...
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... PCI/PCI-Express interfaces. 110 MPC8544E acts as an agent of an external host on its PCI interface. It acts as a root complex for all PCI-Express interfaces. 111 MPC8544E acts as the host processor/root complex on all interfaces (default). Chapter 17, “PCI respectively. Meaning Freescale Semiconductor ...
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... Reset Configuration Signal Name TSEC3_TXD[6:4] cfg_IO_ports[0:2] Default (111) MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-14 Table 4-14. I/O Port Selection Value (Binary) 000 All three PCI Express ports powered down SGMII ports powered down ...
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... SGMII: RX lane[0:1] → SD2_RX[2:3] TX lane[0:1] → SD2_TX[2:3] Table 4-15, specifies the boot configuration mode. If LA27 Section 8.2.1.2, “ECM CCB Port Configuration Section 19.4.1.2, “POR Boot Mode Status (PBFR).”) and the PCI Express Configuration Ready Register—0x4B0.”). Meaning Freescale Semiconductor ...
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... CPU boot configuration signal described in MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-15. CPU Boot Configuration Value (Binary) 0 CPU boot holdoff mode ...
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... Ethernet interface operates in serial SGMII mode. POR config inputs cfg_tsec3_width and cfg_tsec3_prtcl should be left in their default settings. 1 eTSEC3 Ethernet interface uses parallel interface according to POR config inputs cfg_tsec3_width and cfg_tsec3_prtcl. (default). describes the configuration of the DDR Meaning Section 19.4.1.4, “POR Device Meaning Meaning Freescale Semiconductor ...
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... Note that the value latched on these signals during POR is accessible through the memory-mapped PORDEVSR (POR device status register) described in Status Register (PORDEVSR).” MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-20, selects standard versus reduced width for three-speed Value ...
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... The eTSEC3 controller operates using the TBI protocol (or RTBI if configured in reduced mode as described in Width”) (default). Meaning Section 4.4.3.11, “eTSEC1 Section 4.4.3.11, “eTSEC1 Section 4.4.3.11, “eTSEC1 Section 19.4.1.4, “POR Device Meaning Section 4.4.3.12, “eTSEC3 Section 4.4.3.12, “eTSEC3 Section 4.4.3.12, “eTSEC3 Section 19.4.1.26, “SerDes 2 Control Freescale Semiconductor ...
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... Note that the values latched on these signals during POR are accessible through PORIMPSCR, described in Register (PORIMPSCR).” MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Value (Binary) 0 SGMII SerDes expects a 100MHz reference clock frequency (default). ...
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... Debug information from the local bus controller (LBC) is driven on the MSRCID and MDVAL signals 1 Debug information from the DDR SDRAM controller is driven on the MSRCID and MDVAL signals (default). Table 4-30, enables a DDR memory controller debug mode Meaning Meaning Meaning Freescale Semiconductor ...
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... Alternately, a separate, independent clock may be used for the PCI interface, in which case PCI operation is asynchronous with respect to SYSCLK and the platform clock. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 4-30. DDR Debug Configuration Value ...
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... CCB_clk to Rest of the Device Table 4-32. Table 4-32. High Speed Interface Clocking Bit Rate Reference Clock Frequency 2.5 Gbps 100 MHz (Spread Spectrum supported) 1.25 Gbps core_clk 6 MCK[0:5] 6 MCK[0:5] LSYNC_IN LSYNC_OUT LCLK0 LCLK1 LCLK2 100 MHz Freescale Semiconductor DDR Controller LBC ...
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... The default source of the time base is the CCB clock divided by eight. For more details, see the e500 core family reference manual. Section 10.3.2.6, “Timer Control Register signal to clock the global timers in the PIC unit. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor × ( PCI Express link width 8 (TCR),” ...
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... Figure 4-7. RTC and Core Timer Facilities Clocking Options MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 4-26 HID0 TBEN TBL 32 63 • • • Core Timer Facilities Clock • • • (Decrementer) DEC Auto-Reload DECAR 32 63 SEL_TBCLK RTC (Sampled ÷ 8 CCB Clock Freescale Semiconductor ...
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... The e500 core complex interacts with the L2 cache through the core complex bus (CCB). MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor provides an overview of the e500v2 core processor and the provides a listing of the e500v2 registers in reference form. ...
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... Core Complex and L2 Cache MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 II-2 Freescale Semiconductor ...
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... Note that this conceptual diagram does not attempt to show how these features are physically implemented. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor 5-1 ...
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... Core Complex Overview Figure 5-1. e500 Core Complex Block Diagram MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 5-2 Freescale Semiconductor ...
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... Customer software that uses SPE or embedded floating-point instructions at the assembly level or that uses SPE intrinsics will require rewriting for upward compatibility with next-generation PowerQUICC devices. Freescale Semiconductor offers a libcfsl_e500 library that uses SPE instructions. Freescale will also provide libraries to support next-generation PowerQUICC devices. 5.1.2 ...
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... Version Register (PVR),” (SVR)”). Processor Version Register (PVR) 0x8021_0021 0x803C_0110 for MPC8544E (with security) 0x8034_0110 for MPC8544 (without security) 0x8021_0022 0x803C_0111 for MPC8544E (with security) 0x8034_0111 for MPC8544 (without security) Section 6.5.3, “Processor System Version Register (SVR) Freescale Semiconductor ...
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... Figure 5-2. Original SPE Definition MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Section 5.8, “Interrupts and Exception Handling.” NOTE Vector and Floating-Point APUs SPE vector instructions ev… Vector single-precision floating-point evfs… ...
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... Dynamic branch prediction using a 512-entry, 4-way set-associative branch target buffer (BTB) supported by the e500 BTB instructions listed in — Branch prediction is handled in the fetch stages. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 5-6 Figure 5-7. SPE instructions are grouped as follows: Table Table 5-3 5-5. Freescale Semiconductor ...
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... Note that although most divide instructions take more than 4 cycles to execute, the MU allows subsequent multiply instructions to execute through all four MU stages in parallel with the divide. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Figure 5-3. From GIQ0 or GIQ1 ...
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... Station Load/Store Unit (64-/32-Bit) Three-Stage Pipeline Queues and Buffers Load L1 Store Queue Miss Queue Data Line Fill Buffer Data Write e500v1 (3 entry) Buffer e500v2 (5 entry) To core interface unit Figure 5-4. Three-Stage Load/Store Unit To data cache e500v1 (4 entry) e500v2 (9 entry) Freescale Semiconductor ...
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... Support for big-endian and true little-endian memory on a per-page basis • Power management — Low-power design MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Core Complex Overview effective address space physical memory on the e500v1 and 64 ...
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... PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions required to flush the cache. Detailed descriptions of these differences are provided in their respective chapters. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 5-10 Freescale Semiconductor ...
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... Scalar single-precision floating-point instructions use only the lower 32 bits of the GPRs; double-precision operands (e500v2 only) use all 64 bits. floating-point instructions. MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor NOTE - then-else statement that selects between two source registers by Table 5-2 lists performance monitor instructions ...
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... Freescale Semiconductor ...
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... MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1 Freescale Semiconductor Table 5-5. BTB Locking Instructions Name Mnemonic ...
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... General Issue Queue (GIQ) Execute Stage MU Stage 1 Divide Bypass Stage 2 Divide Postdivide Stage 3 Stage 4 Maximum two-instruction Completion Stage completion per clock cycle Write-Back Stage Figure 5-5. Instruction Pipeline Flow 5-5. Instruction Cache Maximum four-instruction fetch per clock cycle SU2 SU1 Freescale Semiconductor ...