MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1239

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MPC8544COMEDEV

Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8544COMEDEV

Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Freescale Semiconductor
LSSD_MODE
L1_TSTCLK
L2_TSTCLK
THERM[0:1]
TEST_SEL
Signal
TRST
TDO
TMS
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
O JTAG test data output.
I
I
I
I
I
I
I
Table 21-5. JTAG Test and Other Signals—Detailed Signal Descriptions
JTAG test mode select.
JTAG test reset.
Used for factory test. Refer to the MPC8544E Integrated Processor Hardware Specifications for proper
treatment.
treatment.
treatment.
The actual value for the resistor varies from device to device, but the linear relationship between
temperature and resistance is consistent. See the Integrated Processor Hardware Specifications for more
information on how to accurately measure the junction temperature of a device. Note that this thermal
resistor is intended for engineering development only.
Used for factory test. Should be negated (pulled high) for normal operation.
Used for factory test. Refer to the MPC8544E Integrated Processor Hardware Specifications for proper
Used for factory test. Refer to the MPC8544E Integrated Processor Hardware Specifications for proper
These signals provide access to an internal resistor that has a value that varies linearly with temperature.
Meaning
Meaning
Meaning
Timing See IEEE 1149.1 standard for more details.
Timing See IEEE 1149.1 standard for more details.
Timing See IEEE 1149.1 standard for more details.
State
State
State
Asserted/Negated—The contents of the selected internal instruction or data register are
Asserted/Negated—Decoded by the internal JTAG TAP controller to distinguish the primary
Asserted—Causes asynchronous initialization of the internal JTAG TAP controller. Must be
Negated— Normal operation.
shifted out on this signal on the falling edge of TCK. Remains in a high-impedance state
except when scanning data.
operation of the test support circuitry. An unterminated input appears as a high signal
level to the test logic due to an internal pull-up resistor.
asserted during power-on reset in order to properly initialize the JTAG TAP and for normal
operation of the MPC8544E. An unterminated input appears as a high signal level to the
test logic due to an internal pull-up resistor.
Description
Debug Features and Watchpoint Facility
21-9

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