MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 590

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Security Engine (SEC) 2.1

The SEC controller generates the single interrupt output from all possible interrupt sources. These sources

can be individually enabled by the interrupt mask register. If enabled, the interrupt source value, when

active, is captured into the interrupt status register.

interrupt source. Each interrupt source is individually enabled by setting its corresponding bit. At reset, all

bits are disabled. The bit fields are described in

interrupt clear register.

Address 0x3_1008

Table 12-60. Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers

describes the register field names in the interrupt mask register, interrupt status register, and

Interrupt Mask Register (IMR)

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Internal time out.

0 No internal time out

1 An internal time out was detected

The internal time out interrupt is triggered by the controller if a slave access to an SEC register does

not result in successful data transfer within 16 clock cycles. With ITO enabled the SEC controller

terminates the transaction and signals and interrupt.

Done overflow.

0 No done overflow

1 Done overflow error. Indicates that more than 15 done interrupts were queued from the interrupting

channel without an interrupt clear.

Figure 12-80. Interrupt Mask Register (IMR)

DONE Overflow

Figure 12-80

shows the bit positions of each potential

Freescale Semiconductor

Access: Read/write