MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 443

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

These addresses, shown in
and are called the private access space. Because this device has only one core, there is only one set of
per-CPU registers, each register having two addresses. For example, the CTPR is located normally at
0x6_0080, and also at the private access address of 0x4_0080. While this double mapping seems
superfluous on a single-core device, the purpose of this feature is to enable user code to execute correctly
in an multiprocessor environment without needing to know which CPU it is running on. It is included on
this device to simplify the porting of such code.
An example of how the different registers are addressed in a four-core device is illustrated in
Note that when accessing a register normally, each core sources a different address. However, when
accessing the same register using the per-CPU address space, each core sources the same address.
10.3.8.1
There are four interprocessor interrupt dispatch registers (IPIDRs), one for each IPI channel, as shown in
Figure
interrupts apparently makes little sense in a single-core device, this feature can serve as a doorbell type
interrupt because external bus masters can write to these registers.
Freescale Semiconductor
10-43. Writing to an IPIDR with a bit set causes a self interrupt. While the concept of interprocessor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3)
Figure 10-42. Per-CPU Register Address Decoding in a Four-Core Device
Uses Core ID
Per-CPU Register
Address Decode
Reg 3
Table
Reg 2
IACK Registers (one per core)
10-46, appear in the memory map at the same offset for every processor,
Reg 1
Reg 0
0x40
0x40
0x40
0x40
ID0
ID1
Address
Normal Register
Address Decode
ID2
Programmable Interrupt Controller
ID3
Processor
Cores
Figure
10-42.
10-45