MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 757

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Each eTSEC can issue three kinds of hardware interrupt to the PIC:
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors are visible to network management via the MIB counters.
Figure 15-4
Table 15-7
Freescale Semiconductor
Offset eTSEC1:0x2_4010; eTSEC3: 0x2_5010
Reset
Reset
Bits
0
1
W
W
1. Transmit interrupts—Issued whenever bits TXB or TXF of IEVENT are set to 1 and either transmit
2. Receive interrupts—Issued whenever bits RXB or RXF of IEVENT are set to 1 and either receive
3. Error and diagnostic interrupts—Issued whenever bits MAG, GTSC, GRSC, TXC, RXC, BABR,
R BABR
R RXB
interrupt coalescing is disabled or the interrupt coalescing thresholds have been met for TXF. To
negate this hardware interrupt, software must clear both TXB and TXF bits.
interrupt coalescing is disabled or the interrupt coalescing thresholds have been met for RXF. To
negate this hardware interrupt, software must clear both RXB and RXF bits.
BABT, LC, CRL, FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN or BSY of IEVENT are set to 1.
Software must clear all of these bits to negate an error/diagnostic hardware interrupt.
— Magic Packet reception event is: MAG
— Operational diagnostics are events on: GTSC, GRSC, TXC and RXC
— Interrupts resulting from errors/problems detected in the network or transceiver are: BABR,
— Interrupts resulting from internal errors are: FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN and
w1c
w1c
16
0
Name
BABR
RXC
BABT, LC and CRL
BSY
describes the fields of the IEVENT register.
describes the definition for the IEVENT register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
RXC
w1c
17
1
maximum frame length register while MACCFG2[Huge Frame] is set.
0 Excessive frame not received.
1 Excessive frame received.
Receive control interrupt. A control frame was received while MACCFG1[Rx_Flow] is set. As soon as the
transmitter finishes sending the current frame, a pause operation is performed.
0 Control frame not received.
1 Control frame received.
Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC’s
BSY
w1c
18
2
—
EBERR
w1c
19
3
Figure 15-4. IEVENT Register Definition
Table 15-7. IEVENT Field Descriptions
MAG MMRD MMWR GRSC RXF
w1c
—
20
4
MSRO
w1c
w1c
21
5
GTSC
w1c
w1c
All zeros
All zeros
22
6
Description
BABT TXC TXE TXB TXF
w1c
w1c
23
7
w1c
w1c
24
8
Enhanced Three-Speed Ethernet Controllers
w1c
25
9
w1c w1c
—
10
26
11
27
w1c w1c w1c
FIR FIQ DPE PERR
—
12
28
w1c w1c
LC CRL XFUN
13
29
Access: w1c
14
30
w1c
w1c
15-25
15
31