MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1004

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
Each window’s base address and translation address must be aligned to the size of the window. If two
general inbound ATMU windows overlap in the external PCI address space, the mappings of the lower
numbered window are applied; PCSRBAR takes priority over any overlapping inbound ATMU window.
In addition, if inbound ATMU windows are overlapped, the ATMU windows must not map to the same
address with different sets of attributes (other than window size).
Note that PCSRBAR in the PCI configuration header acts as a fourth inbound window that translates a
1-Mbyte region of PCI space to the local configuration space pointed to by CCSRBAR. PCSRBAR can
be accessed by PCI configuration cycles or by accessing the PCI configuration header through the PCI
CFG_ADDR and PCI CFG_DATA registers. See
(CFG_ADDR),” Section 17.3.1.1.2, “PCI Configuration Data Register (CFG_DATA),”
Section 17.3.2.11, “PCI Base Address Registers.”
byte lane redirection from the little-endian PCI bus to the big-endian CCSRBAR configuration space.
17.3.1.3.1
The PCI inbound translation address registers (PITARn) points to the beginning of the local address space
for the inbound window. The translated address is created by concatenating the transaction offset to this
translation address. The format of the PITARn is shown in
Table 17-11
17.3.1.3.2
The PCI inbound window base address registers (PIWBARn) select the PCI base address for the windows
that are translated to the internal platform address space. Addresses for inbound transactions are compared
to these windows. If a PCI transaction does not fall within one of these spaces, then the PCI interface does
not assert DEVSEL. The PIWBARn is shown in
17-20
Offset 0xDA0, 0xDC0, 0xDE0
Reset
12–31
W
0–11
R
Bits Name
0
TEA Translation extended address. Bits 0–7 are reserved; bits 8–11 correspond to bits [0:3] of the local
TA
describes the fields of the PITARn registers
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Inbound Translation Address Registers (PITAR n )
PCI Inbound Window Base Address Registers (PIWBAR n )
translation address.
0x000 – 0x00F are valid.
0x010 and greater are reserved.
Translation address. Indicates the starting point of the inbound translated address. The translation
address must be aligned based on the size field. TA corresponds to bits [4:23] of the 36-bit local
translation address.
Figure 17-11. PCI Inbound Translation Address Registers (PITAR n )
TEA
Table 17-11. PITAR n Field Descriptions
11 12
Section 17.3.1.1.1, “PCI Configuration Address Register
Figure
All accesses to PCSRBAR have an automatic internal
All zeros
Description
17-12.
Figure
17-11.
TA
Freescale Semiconductor
Access: Read/Write
and
31