MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 725

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.6.2.2
The synchronous SSRAM-like mode of the DSI is inherently faster than the asynchronous mode and
should be used if larger amounts of data are transferred between the communications controller and the
MSC8102. This will optimize the bus utilization, especially if several MSC8102s are connected to one
local bus. The UPM machine of the LBC must be used to implement this interface.
Figure 14-85
synchronous mode even within a burst transfer on a clock-by-clock basis and because the DSI expects the
host to react within one clock cycle, some tricks can be implemented to support the synchronous mode.
HTA drives LUPWAIT of the UPM. MxMR[UWPL] must be cleared to interpret the correct polarity of
HTA. Because this signal influences the internal state machine of the local bus clock, the local bus cannot
react to HTA changes correctly within one local bus clock. Refer to
(WAEN),”
The solution to this lies in that the local bus operates at a higher frequency than the DSI interface of the
DSP. The local bus clock can be divided by an integer divider (1:2, 1:3, or 1:4) to generate the DSI clock.
This should not be a problem because the local bus is designed for much higher frequencies than the DSI.
Because all timings are given in DSP DSI clock cycles, the UPM patterns must be adjusted appropriately
and need to assert a signal for 2, 3, or 4 clocks (as many as the divider ratio) instead of one. Fortunately,
the UPM has the REDO feature, which allows every UPM RAM entry to be executed 1×, 2×, 3×, or 4×,
which should be sufficient for any divider ratio that would be used in this case.
Freescale Semiconductor
for more detailed information.
Legend:
HWBS[0:7]
HDST[0:1]
Timing conventions:
HA[11:29]
HCID[0:3]
1
0
1
0
HD[0:63]
shows the interface for synchronous mode. Because the DSI will assert and negate HTA in
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
HRDS
DSI in Synchronous Mode
HCS
HTA
Valid value that can be 1 or 0
Don’t care
Three-state output signal that is not driven by the DSI
Figure 14-84. Asynchronous Read from MSC8102 DSI
HTAAD = 1 & HTADT = 01,10,11
HTAAD = 0 & HTADT = 00
Section 14.4.4.4.10, “Wait Mechanism
Local Bus Controller
14-105