MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1241

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.1
The following sections describe the control registers for the watchpoint monitor facility.
21.3.1.1
The watchpoint monitor control registers (WMCR0, WMCR1) shown in
control the specification of watchpoint monitor events.
Table 21-7
Freescale Semiconductor
0xE_20B0 TOSR—Trigger output source register
Offset 0x000
Reset
Memory
Bits
Offset
Local
0
1
2
3
W
R
EN AMD TMD ECEN NECEN SIDEN TIDEN
0
ECEN Equal context enable. Qualifies the matching of current context with programmed context as a watchpoint
Name
AMD
TMD
EN
describes WMCR0 fields.
Watchpoint Monitor Register Descriptions
1
Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Enable
0 Watchpoint monitor events are not flagged.
1 A watchpoint monitor event is flagged.
Address match disable. Qualifies address match as a watchpoint event criterion.
0 Address matching is used to recognize a watchpoint event.
1 Address matching does not affect watchpoint event detection.
Transaction match disable. Qualifies transaction type match (as defined in WMCR1[IFSEL] and WMTMR) as
a watchpoint event criterion.
0 A transaction type match is used to recognize watchpoint events.
1 A transaction type match does not affect watchpoint event detection.
event criterion, as written in the context registers described in
0 Current context match does not affect watchpoint event detection.
1 Watchpoint events are qualified by comparing current context with the programmed context event value.
Note: ECEN and NECEN must not be enabled in the same run. If both are set, watchpoint events are
2
Table 21-6. Debug and Watchpoint Monitor Memory Map (continued)
inhibited (never occur).
Figure 21-2. Watchpoint Monitor Control Register 0 (WMCR0)
3
4
Table 21-7. WMCR0 Field Descriptions
Register
5
6
Other Registers
7
All zeros
Description
—
Access
Section 21.3.3, “Context ID Registers.”
R/W
Figure 21-2
Debug Features and Watchpoint Facility
0x0000_0000
20 21
Reset
STRT
23 24
and
Access: Read/Write
Figure 21-3
21.3.4.1/21-24
Section/Page
—
21-11
31