MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 759

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
17–19
25–27
Bits
14
15
16
20
21
22
23
24
28
MMWR MII management write completion
MMRD
GRSC
Name
XFUN
MAG
RXB
CRL
RXF
FIR
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
the MAC’s half-duplex register’s retransmission maximum count (HAFDUP[Retransmission Maximum]). The
frame is discarded without being transmitted and transmission of the next frame commences. This only
occurs while in half-duplex mode.
0 Successive transmission collisions do not exceed maximum.
1 Successive transmission collisions exceed maximum.
was transmitted.
0 Transmit FIFO not underrun.
1 Transmit FIFO underrun.
set in its status word and was not the last buffer descriptor of the frame.
0 Receive buffer descriptor not updated.
1 Receiver buffer descriptor updated.
Reserved
Magic Packet detected when the eTSEC is in Magic Packet detection mode (MACCFG2[MPEN] = 1).
0 No Magic Packet received, or Magic Packet mode was not enabled.
1 A Magic Packet was received while in Magic Packet mode. MACCFG2[MPEN] is also cleared upon
MII management read completion
0 MII management read not issued or in process.
1 MII management read completed that was initiated by a user through the MII Scan or Read cycle
0 MII management write not issued or in process.
1 MII management write completed that was initiated by a user write to the MIIMCON register.
the user to know if the system has completed the stop and it is safe to write to receive registers (status,
control or configuration registers) that are used by the system during normal operation.
0 Graceful stop not completed.
1 Graceful stop completed.
(RxBD) in that frame was updated. This occurs either if the I (interrupt) bit in the buffer descriptor status word
is set, or an overrun error occurs. The specific receive queue that was updated has its RXF bit set in RSTAT.
0 Frame not received.
1 Frame received.
Reserved
The receive queue filer result is invalid, either because not enough time between frames was available to
find a matching rule, or no entry in the filer table could be matched.
0 Receive queue filer reached a definite result; however, bit FIQ may still be set if a frame was filed to a
1 Receive queue filer was unable to reach a definite result. In this case, bit FIQ will also be set if no entry
Collision retry limit. This bit indicates that the number of successive transmission collisions has exceeded
Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame
Receive buffer. This bit indicates that a receive buffer descriptor was updated which had the I (Interrupt) bit
Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It allows
Receive frame interrupt. This bit indicates that a frame was received and the last receive buffer descriptor
receiving the Magic Packet.
command.
disabled RxBD ring.
in the filer table could provide a rule match.
Table 15-7. IEVENT Field Descriptions (continued)
Description
Enhanced Three-Speed Ethernet Controllers
15-27