MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1010

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
17.3.1.4.3
Table 17-17
core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by
clearing HID1[RFXE]). If RFXE is zero and this error occurs, the appropriate parity detect and
master-abort bits in ERR_DR must be cleared and the appropriate enable bits in ERR_EN must be set to
ensure that an interrupt is generated. For more information, see
Implementation-Dependent Register 1 (HID1).”
17-26
Offset 0xE08
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
Bits
23
24
25
26
27
28
29
30
31
error enable
Trgt PERR
16
24
0
8
Mstr PERR error capture disable Disable capture for master PERR errors
Trgt PERR error capture disable Disable capture for target PERR errors
Mstr abort error capture disable
Trgt abort error capture disable
OWMSV error capture disable
ORMSV error capture disable
IRMSV error capture disable
SCM error capture disable
TOE error capture disable
describes ERR_EN fields. Note that uncorrectable read errors may cause the assertion of
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Error Enable Register (ERR_EN)
error enable
Mstr abort
25
Name
Table 17-16. ERR_CAP_DR Field Descriptions (continued)
Figure 17-17. PCI Error Enable Register (ERR_EN)
error enable
Trgt abort
26
—
Disable capture for master abort errors
Disable capture for target abort errors
Disable capture for outbound write memory space violation errors
Disable capture for outbound read memory space violation errors
Disable capture for inbound read memory space violation errors
Disable capture for split completion message errors
Disable capture for time-out errors
OWMSV error
enable
27
All zeros
All zeros
All zeros
All zeros
—
—
ORMSV error
enable
20
28
Section 6.10.2, “Hardware
Description
IRMSV error
error enable
Addr parity
enable
21
29
Rcvd SERR
error enable
SCM error
Freescale Semiconductor
enable
22
30
Access: Read/Write
error enable
Mstr PERR
TOE error
enable
15
23
31
7