MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 280

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM

The following sections describe registers that control and configure the L2/SRAM array.

The L2 control register (L2CTL), shown in

L2/SRAM array. The sequence for modifying L2CTL is as follows:

Offset 0x2_0000

3. stw (WIMG = 01xx) CCSRBAR+0x2_0000

4. lwz (WIMG = 01xx) CCSRBAR+0x2_0000

describes L2CTL fields.

L2/SRAM Register Descriptions

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

L2 Control Register (L2CTL)

L2 enable. Used to enable the L2 array (cache or memory-mapped SRAM).

0 The L2 SRAM (cache and memory-mapped SRAM) is disabled and is not accessed for reads,

1 The L2 SRAM (cache or memory-mapped SRAM) is enabled.

Note that L2I can be set regardless of the value of L2E.

L2 flash invalidate.

0 The L2 status and LRU bits are not being cleared.

1 Setting L2I invalidates the L2 cache globally by clearing the all the L2 status bits, as well as the LRU

Data to memory-mapped SRAM are unaffected by the flash invalidate. The hardware automatically

clears L2I when the invalidate is complete.

L2 SRAM size (read only). Indicates the total available size of on-chip memory array (to be configured

as cache or memory-mapped SRAM).

01 256 Kbyte

snoops, or writes. Setting the L2 flash invalidate bit (L2I) is allowed.

algorithm. Memory-mapped SRAM is unaffected.

Figure 7-7. L2 Control Register (L2CTL)

Table 7-4. L2CTL Field Descriptions

L2LFR L2LFRID

7-7, controls configuration and operation of the

Freescale Semiconductor

Access: Read/Write