MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 806

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers

The MIIMCOM register is written by the user.

Offset eTSEC1:0x2_4524

Reset Mgmt Reset management. This bit is cleared by default.

describes the fields of the MIIMCFG register.

describes the fields of the MIIMCOM register.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

MII Management Command Register (MIIMCOM)

0 Allow the MII MGMT to perform mgmt read/write cycles if requested via the host interface.

1 Reset the MII MGMT.

Preamble suppress. This bit is cleared by default.

0 The MII MGMT performs Mgmt read/write cycles with 32 clocks of preamble.

1 The MII MGMT suppresses preamble generation and reduces the Mgmt cycle from 64 clocks to 32

This field determines the clock frequency of the MII management clock (EC_MDC). Its default value is

Note: The eTSEC system clock is derived from (CCB Clock)/2.

000 1/4 of the eTSEC system clock divided by 8

001 1/4 of the eTSEC system clock divided by 8

010 1/6 of the eTSEC system clock divided by 8

011 1/8 of the eTSEC system clock divided by 8

100 1/10 of the eTSEC system clock divided by 8

101 1/14 of the eTSEC system clock divided by 8

110 1/20 of the eTSEC system clock divided by 8

111 1/28 of the eTSEC system clock divided by 8

clocks. This is in accordance with IEEE 802.3/22.2.4.4.2.

Figure 15-42. MIIMCOM Register Definition

Table 15-44. MIIMCFG Field Descriptions

Table 15-45. MIIMCOM Descriptions

Figure 15-42

describes the definition for MIIMCOM.

Freescale Semiconductor

Access: Read/Write