MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 659

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-24
14.4.2.2
The banks selected to work with the GPCM support an option to drive the LCSn signal with different
timings (with respect to the external address/data bus). LCSn can be driven in any of the following ways:
Freescale Semiconductor
•
1
Simultaneous with the latched memory address. (This refers to the externally latched address, not
the address timing on LAD[0:31]. That is, chip select does not assert during LALE).
TRLX
Total cycles when LALE is asserted for one cycle only (OR n [EAD] = 0; OR n [EAD] = 1 and
LCRR[EADC] = 01). Asserting LALE for more than one cycle increases the total cycle count accordingly.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
shows the signal behavior and system response for a read access.
Option Register Attributes
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Chip-Select Assertion Timing
EHTR
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
XACS
Table 14-24. GPCM Read Control Signal Timing
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
ACS
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
00
10
11
LCS n Asserted
Address to
1+1/4
1+1/2
1+1/4
1+1/2
1/4
1/2
1/4
1/2
0
0
1
2
0
0
1
2
0
0
2
3
0
0
2
3
Signal Behavior (Bus Clock Cycles)
LCS n Negated to
Address Change
1
1
1
1
1
1
2
2
2
2
2
2
5
5
5
5
5
5
9
9
9
9
9
9
Total Cycles
10+2*SCY
12+2*SCY
13+2*SCY
13+2*SCY
12+2*SCY
13+2*SCY
14+2*SCY
8+2*SCY
9+2*SCY
9+2*SCY
8+2*SCY
9+2*SCY
4+SCY
4+SCY
4+SCY
4+SCY
4+SCY
5+SCY
5+SCY
5+SCY
5+SCY
5+SCY
5+SCY
6+SCY
Local Bus Controller
1
14-39