MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 693

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose

some non-zero combination of ORn[TRLX] and ORn[EHTR]. The next accesses after a read access to the

slow memory device is delayed by the number of clock cycles specified in the ORn register in addition to

any existing bus turn around cycle.

Connecting the local bus UPM controller to a DRAM device requires a detailed examination of the timing

diagrams representing the possible memory cycles that must be performed when accessing this device.

This section shows timing diagrams for various UPM configurations, using fast-page mode DRAM as an

example, with LCRR[CLKDIV] = 4(clock ratio of 8) or 8(clock ratio of 16). These illustrative examples

may not represent the timing necessary for any specific device used with the LBC. Here, LGPL1 is

programmed to drive R/W of the DRAM, although any LGPLn signal may be used for this purpose.

Freescale Semiconductor

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Extended Hold Time on Read Accesses

Memory System Interface Example Using UPM

Local Bus Controller