MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1227

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Noncore write misses cache external
write window and SRAM memory range
Non-core read hit in L2
Non-core read miss in L2
L2 allocates, from any source
L2 retries due to full write queue
L2 retries due to address collision
L2 failed lock attempts due to full set
L2 victimizations of valid lines
L2 invalidations of lines
L2 clearing of locks
External event
Watchpoint monitor hits
Trace buffer hits
UART0 baud rate
UART1 baud rate
PMC0 carry-out
PMC1 carry-out
PMC2 carry-out
PMC3 carry-out
PMC4 carry-out
PMC5 carry-out
PMC6 carry-out
PMC7 carry-out
PMC8 carry-out
PMC9 carry-out
Event Counted
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 20-10. Performance Monitor Events (continued)
Number
C7:116
C1:118
C2:124
C3:122
C4:122
C5:116
C6:121
C7:117
C3:125
C2:125
C1:122
C1:127
C5:127
Ref:24
Ref:25
Ref:10
Ref:1
Ref:2
Ref:3
Ref:4
Ref:5
Ref:6
Ref:7
Ref:8
Ref:9
Chaining Events
DUART Events
Debug Events
—
—
—
—
—
—
—
—
—
—
Number of cycles trig_in pin is asserted
—
—
—
—
PMC0[0] 1-to-0 transitions.
PMC1[0] 1-to-0 transitions. Reserved for PMC1.
PMC2[0] 1-to-0 transitions. Reserved for PMC2.
PMC3[0] 1-to-0 transitions. Reserved for PMC3.
PMC4[0] 1-to-0 transitions. Reserved for PMC4.
PMC5[0] 1-to-0 transitions. Reserved for PMC5.
PMC6[0] 1-to-0 transitions. Reserved for PMC6.
PMC7[0] 1-to-0 transitions. Reserved for PMC7.
PMC8[0] 1-to-0 transitions. Reserved for PMC8.
PMC9[0] 1-to-0 transitions. Reserved for PMC9.
Description of Event Counted
Device Performance Monitor
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