MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1008

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

PCI Bus Interface

For an inbound configuration write transaction with a parity error, the device always updates the register

access and generates the error interrupt if the interrupt enabled bit is set.

core_fault_in, which causes the core to generate a machine check interrupt, unless it is disabled (by

clearing HID1[RFXE]). If RFXE is zero and an error occurs, the appropriate parity detect and master-abort

bits in ERR_DR must be cleared and the appropriate enable bits in ERR_EN must be set to ensure that an

interrupt is generated. See

Section 17.4.2.13, “PCI Error Functions,”

Offset 0xE00

describes ERR_DR fields. Note that uncorrectable read errors may cause the assertion of

Multiple PCI

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

PCI Error Detect Register (ERR_DR)

Multiple PCI errors 0 Multiple PCI errors of the same type were not detected (write-1-to-clear)

Addr Parity error

Rcvd SERR error

Mstr PERR error

Section 6.10.2, “Hardware Implementation-Dependent Register 1 (HID1).”

Figure 17-15. PCI Error Detect Register (ERR_DR)

Table 17-15. ERR_DR Field Descriptions

1 Multiple PCI errors of the same type were detected

Address parity error (write-1-to-clear)

Received SERR error (write-1-to-clear)

Master PERR error (write-1-to-clear)

for more detail on error handling.

Freescale Semiconductor