MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1187

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4.1.20 DDR Calibration Status Register (DDRCSR)
Shown in
Table 19-23
19.4.1.21 DDR Control Driver Register (DDRCDR)
Shown in
SDRAM controller.
Freescale Semiconductor
Offset 0xE_0B24
Reset
Offset 0xE_0B20
Reset
10–31
Bits
0–1
2–5
6–9
W
R
W
R DDRDC
DHC_EN DSO_EN DSO_PZ DSO_NZ DSO_PZ_OE DSO_NZ_OE ODT
0
0
Figure
Figure
describes the bit settings of DDRCSR.
1
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DDRDC
Name
19-20, the DDRCSR contains debug status bits from the DDR SDRAM controller.
19-21, the DDRCDR contains bits that allow control over the I/O drivers of the DDR
2
PZ
NZ
—
1
PZ
Figure 19-20. DDR Calibration Status Register (DDRCSR)
2
Figure 19-21. DDR Control Driver Register (DDRCDR)
5
DDR driver compensation input value.
This field reflects the current state of the MDIC[0:1] driver impedance calibration signals.
Current setting of PFET driver impedance (Field values not defined below are reserved.)
0000 Highest impedance; half strength
1000 Higher impedance
1100 Nominal impedance
1110 Lower impedance
1111 Lowest impedance; double strength
Current setting of NFET driver impedance (Field values not defined below are reserved.)
0000 Highest impedance; half strength
1000 Higher impedance
1100 Nominal impedance
1110 Lower impedance
1111 Lowest impedance; double strength
Reserved
6
5 6
Table 19-23. DDRCSR Field Descriptions
NZ
9
9
10
10
All zeros
All zeros
11
Description
12
—
13
—
Access: Read Only
Access: Read/Write
Global Utilities
19-21
31
31