MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1231

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21
Debug Features and Watchpoint Facility
This chapter describes all customer-visible debug modes of the MPC8544E integrated device. The debug
features on the MPC8544E pertain to these interfaces: the local bus controller (LBC), and the DDR
SDRAM interface. In addition to the external interfaces, the MPC8544E provides triggering capabilities
based on user-programmable events. The watchpoint and trace buffer also provide some visibility to
internal buses. This chapter also describes context ID registers, useful for software debug, and describes
the JTAG access port signals that comply with the IEEE 1149.1 boundary-scan specification.
21.1
As shown in the block diagram of
features (listed with references to sections of this chapter that describe them):
21.1.1
As shown in
SDRAM. Limited visibility, through a 256 x 64 trace buffer, is also provided for the processor core
interface. This visibility into internal device operation is useful for debugging application software through
inverse assembly and reconstruction of the fetch stream.
The combination of a source ID (MSRCID[0:4]) and a data-valid signal (MDVAL) indicates that
meaningful debug information is visible on either the local bus or DDR SDRAM interfaces. A logic
analyzer can be programmed to capture data based on the values of MSRCID[0:4] and MDVAL.
Freescale Semiconductor
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DDR SDRAM interface debug
Local bus controller (LBC) debug
Watchpoint monitor and trace buffer debug
Section 21.4.5, “Trace
Introduction
Overview
Figure
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
21-1, debug information is provided through the following interfaces: LBC, and DDR
Buffer”)
Figure
(Section 21.4.2, “DDR SDRAM Interface
21-1, the MPC8544E device provides the following debug
(Section 21.4.3, “Local Bus Interface
(Section 21.4.4, “Watchpoint Monitor,”
Debug”)
Debug”)
and
21-1