MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 274

no-image

MPC8544COMEDEV

Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8544COMEDEV

Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
L2 Look-Aside Cache/SRAM
7.2
The on-chip memory array has four banks, each containing 256 sets of eight cache blocks (or ‘ways’), as
shown in
7-4
Bank 0
Figure
L2 Cache and SRAM Organization
Way 0
Way 1
Way 2
Way 3
Way 4
Way 5
Way 6
Way 7
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
7-2. Each block consists of 32 bytes of data and a tag.
256 Sets
Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
Address Tag 4
Address Tag 5
Address Tag 6
Address Tag 7
Bank 3
Way 0
Way 1
Way 2
Way 3
Way 4
Block 5
Block 6
Block 7
256 Sets
Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
Address Tag 4
Address Tag 5
Address Tag 6
Address Tag 7
Figure 7-2. Cache Organization
8 Words/Block
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
8 Words/Block
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Words [0–7]
Freescale Semiconductor

Related parts for MPC8544COMEDEV