MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 250

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MPC8544COMEDEV

Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets

Specifications of MPC8544COMEDEV

Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Core Register Summary
6.12
6.12.1
6.12.2
6.12.3
6-32
Reset
Reset
Reset 0 0 0 0
32–60
SPR 1012
SPR
SPR
SPR
SPR 1015
Bits
61
62
63
W
W
R
W
R
R
32
48 (PID0)
633 (PID1)
634 (PID2)
32
32
L2TLB0_FI TLB0 flash invalidate (write to 1 to invalidate)
L2TLB1_FI TLB1 flash invalidate (write 1 to invalidate)
Name
MMU Registers
Process ID Registers (PID0–PID2)
MMU Control and Status Register 0 (MMUCSR0)
MMU Configuration Register (MMUCFG)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 0 0 0 0
Reserved, should be cleared.
0 No flash invalidate. Writing a 0 to this bit during an invalidation operation is ignored.
1 TLB1 invalidation operation. Hardware initiates a TLB1 invalidation operation. When this operation is
Reserved, should be cleared.
complete, this bit is cleared. Writing a 1 during an invalidation operation causes an undefined
operation.
Figure 6-39. MMU Control and Status Register 0 (MMUCSR0)
Figure 6-40. MMU Configuration Register (MMUCFG)
Figure 6-38. Process ID Registers (PID0–PID2)
Table 6-24. MMUCSR0 Field Descriptions
0 0 0 0 0
0 0 0 0 0
All zeros
All zeros
48 49
Description
NPIDS
1 1 0 0 1
52 53
PIDSIZE
55 56
1 1 0 0
Access: Supervisor read/write
Access: Supervisor read/write
60
Access: Supervisor read only
57 58 59
L2TLB0_FI L2TLB1_FI —
Freescale Semiconductor
61
Process ID
NTLBS
60
0
61
1
62
62
MAVN
0
63
63
0
63

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