MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1332

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index-16
e500 core, see e500 core, registers
ECM, 8-3
eTSEC, 15-23–15-127
global utilities, 19-4
I
L2 cache/SRAM registers, 7-8–7-25
LBC, 14-10
local access window registers
PCI Express
2
C interface, 11-5
configuration registers, 9-11–9-32
error handling registers, 9-34–9-41
error injection registers, 9-33–9-34
DMA attribute registers, 15-111–15-113
FIFO registers, 15-110–15-111
general control and status registers, 15-23–15-37
hash function registers, 15-108–15-109
lossless flow control registers, 15-113–15-115
MAC registers, 15-67–15-80
MIB registers, 15-80–15-108
receive control and status registers, 15-49–15-64
ten-bit interface registers, 15-116–15-127
transmit control and status registers, 15-37–15-49
POR boot mode status, 19-6
POR debug mode status, 19-10
POR device status, 19-8
POR external system configuration, 19-11
POR I/O impedance status, 19-7
POR PLL status, 19-4
attributes registers (LAWAR0–LAWAR7), 2-7
base address registers (LAWBAR0–LAWBAR7), 2-7
configuration header registers, 18-43–18-66
32-bit memory base address register, 18-51
64-bit high memory base address register, 18-52
64-bit low memory base address register, 18-52
base address registers, 18-50–18-52, 18-57
bridge control register, 18-66
bus status register, 18-46
cache line size register, 18-48
capabilities pointer register, 18-54, 18-64
command register, 18-44
configuration and status register base address
device ID register, 18-44, 18-53
I/O base register, 18-59
I/O base upper 16 bits register, 18-63
I/O limit register, 18-59
I/O limit upper 16 bits register, 18-64
interrupt line register, 18-54, 18-65
interrupt pin register, 18-55, 18-65
latency timer register, 18-49, 18-59
maximum latency (EP-mode) register, 18-56
memory base register, 18-61
(PCSRBAR), 18-50, 18-57
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
device-specific configuration space registers,
extended configuration space registers, 18-81–18-89
memory-mapped registers
memory limit register, 18-61
minimum grant (EP-mode) register, 18-55
prefetchable base upper 32 bits register, 18-63
prefetchable limit upper 32 bits register, 18-63
prefetchable memory base register, 18-62
prefetchable memory limit register, 18-62
primary bus number, 18-57
revision ID register, 18-47
secondary bus number, 18-58
secondary status register, 18-60
subordinate bus number, 18-58
subsystem vendor ID, 18-53
vendor ID, 18-44
capabilities register, 18-70
capability ID register, 18-70
device capabilities register, 18-71
device control register, 18-71
device status register, 18-72
link capabilities register, 18-73
link control register, 18-73
link status register, 18-74
MSI message address register, 18-79
MSI message capability ID register, 18-78
MSI message control register, 18-78
MSI message data register, 18-80
MSI message upper address register, 18-79
power management capabilities register, 18-68
power management capability ID register, 18-68
power management data register, 18-69
power management status and control register, 18-69
root control register, 18-77
root status register, 18-78
slot capabilities register, 18-75
slot control register, 18-76
slot status register, 18-76
advanced error capabilities and control register, 18-86
advanced error reporting capability ID register, 18-82
correctable error mask register, 18-85
correctable error source ID register, 18-89
correctable error status register, 18-85
error source ID register, 18-89
header log register, 18-87
root error command register, 18-88
root error status register, 18-88
uncorrectable error mask register, 18-83
uncorrectable error severity register, 18-84
uncorrectable error status register, 18-82
ATMU registers, 18-19–18-29
18-67–18-80
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