MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1322

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index-6
functional description, 15-127
gigabit Ethernet channel operation, 15-141
hash function
initialization/application information, 15-179–15-209
interrupts, 15-152–15-155
lossless flow control, 15-170
MAC functionality, 15-65–15-80
memory map/register definition, 15-13
modes of operation, 15-4
overview, 1-18, 15-1
physical interface connections, 15-127
quality of service (QoS) support, 15-162–15-170
flow control, 15-151
frame reception, 15-144
frame recognition, 15-147
frame transmission, 15-143
initialization sequence, 15-141
internal and external loop back, 15-155
inter-packet gap time, 15-155
Magic Packet mode, 15-151
preamble customization, 15-145
RMON support, 15-147
algorithm, 15-149
registers, 15-108–15-109
gigabit Ethernet channel, 15-141
see also eTSEC, configuration
interrupt coalescing, 15-153
interrupt registers, 15-24–15-30
back pressure determination and free buffers, 15-170
software use of hardware-initiated back pressure, 15-172
configuration, 15-65
CSMA/CD control, 15-65
handling packet collisions, 15-65
packet flow control, 15-66
PHY links control, 15-67
registers, 15-67–15-80
detailed memory map, 15-14–15-23
eTSEC2–4 controller offsets, 15-23, B-40
top-level module map, 15-13
RMON support, 15-80
gigabit media-independent interface (GMII), 15-129
media-independent interface (MII), 15-128
reduced gigabit media-independent interface (RGMII),
reduced media-independent interface (RMII), 15-128
reduced ten-bit interface (RTBI), 15-132
ten-bit interface (TBI), 15-131
receive queue filer, 15-162
soft reset and reconfiguring procedure, 15-142
soft reset and reconfiguring procedure, 15-142
by frame count threshold, 15-153
by timer threshold, 15-154
15-129
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
eTSEC2 signals as GP I/O, see Global utilities,
External system configuration
External writes, see L2 cache/SRAM, stashing
F
Full-on mode (power), 1-20
G
General-purpose I/O (PCI and eTSEC2)
Global utilities
register descriptions, 15-23–15-127
signals, 15-6–15-12
TCP/IP off-load, 15-157–15-162
POR (LAD[0:31]) status, 4-23, 19-11
see Global utilities
clock out
DDR calibration status, 19-21
DDR controller
DMA signal multiplex control register (PMUXCR), 19-13,
features, 19-1
functional description, 19-27
general-purpose I/O signals (PCI and eTSEC2)
transmission scheduling, 15-168
by acronym, see Register Index
DMA attribute registers, 15-111–15-113
FIFO registers, 15-110–15-111
general control and status registers, 15-23–15-37
hash function registers, 15-108–15-109
lossless flow control registers, 15-113–15-115
MAC registers, 15-67–15-80
MIB registers, 15-80–15-108
receive control and status registers, 15-49–15-64
ten-bit interface registers, 15-116–15-127
transmit control and status registers, 15-37–15-49
FIFO interface signal summary, 15-140
see also Signals, eTSEC
summary, 15-6
frame control blocks, 15-158
receive path off-load, 15-160
transmit path off-load, 15-158
general-purpose I/O signals
CLK_OUT signal, 19-3, 19-23
clock out control register (CLKOCR), 19-23
overview, 19-1
clock disable, 19-22
control register (GPIOCR), 19-11
GPOUT[24:31] signals, 19-3
input data register (GPINDR), 19-13
operation of, 19-35
output data register (GPOUTDR), 19-12
19-35
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