MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 688

Manufacturer Part Number

MPC8544COMEDEV

KIT DEV EXPRESS MPC8544COM

Manufacturer

Freescale Semiconductor

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Local Bus Controller

signal of the corresponding bank depends on the value of each CSTn bit.

control LCSn signals.

If BRn[MSEL] of the accessed memory bank selects a UPM on the currently requested cycle, the selected

UPM affects the assertion and negation of the appropriate LBS[0:3] signal. The timing of all four

byte-select signals is specified in the RAM word. However, LBS[0:3] are also controlled by the port size

of the accessed bank, the number of bytes to transfer, and the address accessed.

Figure 14-60

The uppermost byte select (LBS0), when asserted, indicates that LAD[0:7] contains valid data during a

cycle. Likewise, LBS1 indicates that LAD[8:15] contains valid data, LBS2 indicates that LAD[16:23]

contains valid data, and LBS3 indicates that LAD[24:31] contains valid data. For a UPM refresh timer

request, all LBS[0:3] signals are asserted/negated by the UPM according to the refresh pattern only.

shows how UPMs control LBS[0:3].

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Byte Select Signal Timing (BST n )

Figure 14-59. LCS n Signal Selection

Figure 14-60. LBS Signal Selection

Bank Selected

Bank Selected

Figure 14-59

Freescale Semiconductor

shows how UPMs