MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 353

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.1.12
The DDR SDRAM interval configuration register, shown in
cycles between bank refreshes issued to the DDR SDRAMs. In addition, the number of DRAM cycles that
a page is maintained after it is accessed is provided here.
Table 9-18
9.4.1.13
The DDR SDRAM data initialization register, shown in
to initialize memory if DDR_SDRAM_CFG2[D_INIT] is set.
Table 9-19
Freescale Semiconductor
16–17
18–31 BSTOPRE Precharge interval. Sets the duration (in memory bus clocks) that a page is retained after a DDR SDRAM
0–15
Bits
0–31
Bits
Offset 0x124
Offset 0x128
Reset
Reset
W
W
R
REFINT
R
INIT_VALUE Initialization value. Represents the value that DRAM will be initialized with if
Name
—
0
0
Figure 9-14. DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)
Name
Figure 9-13. DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
describes the DDR_SDRAM_INTERVAL fields.
describes the DDR_DATA_INIT fields.
DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL)
DDR SDRAM Data Initialization (DDR_DATA_INIT)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each DDR SDRAM physical bank
during each refresh cycle. The value for REFINT depends on the specific SDRAMs used and the interface
clock frequency. Refreshes will not be issued when the REFINT is set to all 0s.
Reserved
access. If BSTOPRE is zero, the DDR memory controller uses auto-precharge read and write commands
rather than operating in page mode. This is called global auto-precharge mode.
DDR_SDRAM_CFG2[D_INIT] is set.
Table 9-18. DDR_SDRAM_INTERVAL Field Descriptions
Table 9-19. DDR_DATA_INIT Field Descriptions
REFINT
INIT_VALUE
All zeros
All zeros
Description
15 16 17 18
Figure
Description
Figure
—
9-14, provides the value that will be used
9-13, sets the number of DRAM clock
BSTOPRE
Access: Read/Write
Access: Read/Write
DDR Memory Controller
31
31
9-29