MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1016
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MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PCI Bus Interface
17.3.2.4
The 2-byte PCI bus status register is used to record status information for PCI bus-related events. The
definition of each bit is given in
Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set.
A bit is cleared whenever the register is written, and the data in the corresponding bit location is a 1. For
example, to clear bit 14 without affecting any other bits in the register, write the value
0b0100_0000_0000_0000 to the register.
17-32
Bits
8
7
6
5
4
3
2
1
0
Memory-write-
Special-cycles Hard-wired to 0, indicating that this PCI controller (as a target) ignores all special-cycle
and-invalidate
Bus master
Parity error
I/O space
response
Memory
PCI Bus Status Register—Offset 0
Name
SERR
space
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
Table 17-26. PCI Bus Command Register Field Descriptions (continued)
Controls the PCI_SERR driver of this PCI controller. This bit (and bit 6) must be set to report
address parity errors.
0 Disables the PCI_SERR driver
1 Enables the PCI_SERR driver
Reserved
Controls whether this PCI controller responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Parity errors cause the appropriate bit in the PCI status register to be set. However, note that
Reserved
Hard-wired to 0, indicating that this PCI controller, acting as a master, can not generate the
memory-write-and-invalidate command.
commands.
Indicates whether this PCI controller is configured as a master. This indicates the setting of the
host/agent configuration input signal at power-on reset.
0 Disables the ability to generate PCI accesses
1 Enables this PCI controller to behave as a PCI bus master (Host)
Controls whether this PCI controller (as a target) responds to memory accesses.
0 This PCI controller does not respond to PCI memory space accesses.
1 This PCI controller (as a target) responds to PCI memory space accesses.
Hard-wired to 0, indicating that this PCI controller (as a target) does not respond to PCI I/O
space accesses.
errors are reported based on the values set in the PCI error enable and detection registers.
Table
17-27. Only 2-byte accesses to address offset 0x06 are allowed.
Description
x
06
Freescale Semiconductor
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