MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 248
MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (12Mb)
Core Register Summary
6.11.3
6-30
Reset 0
56–61
32–33
34–38
39–40
41–42
SPR 515
Bits
Bits
53
54
55
62
63
43
W
R CARCH
32
ICLFR Instruction cache lock bits flash reset. Writing 0 and then 1 flash clears the lock bit of all entries in the
Name
ICUL
ICLO
CBSIZE
CARCH
ICFI
ICE
CREPL
Name
—
33
CLA
0
—
L1 Cache Configuration Register 0 (L1CFG0)
34
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 0 0 0 0
Instruction cache unable to lock. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock set instruction was effective in the instruction cache
1 Indicates a lock set instruction was not effective in the instruction cache
Instruction cache lock overflow. Sticky bit set by hardware and cleared by writing 0 to this bit location.
0 Indicates a lock overflow condition was not encountered in the instruction cache
1 Indicates a lock overflow condition was encountered in the instruction cache
instruction cache; clearing occurs independently from the value of the enable bit (ICE). ICLFR is always read
as 0.
Reserved, should be cleared.
Instruction cache flash invalidate. Written to 0 and then 1 to flash clear the valid bit of all entries in the
instruction cache; operates independently from the value of the enable bit (ICE). ICFI is always read as 0.
Instruction cache enable
0 The instruction cache is neither accessed or updated.
1 Enables instruction cache operation
Cache architecture
00 Harvard
01 Unified
Reserved, should be cleared.
Cache line size
0 32 bytes
1 64 bytes
Cache replacement policy
0 True LRU
1 Pseudo LRU
Cache locking available
0 Unavailable
1 Available
—
Figure 6-36. L1 Cache Configuration Register 0 (L1CFG0)
38
Table 6-21. L1CSR1 Field Descriptions (continued)
CBSIZE CREPL CLA CPA
39
0
40
0
Table 6-22. L1CFG0 Field Descriptions
41
0
42
1
43
1
44
1
45
0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0
Description
Description
—
49 50 51 52 53
CNWAY
—
55 56
Freescale Semiconductor
Access: User read only
CSIZE
63
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