MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 116

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview
machine can optimize burst transfers and exploits interleaving to maximize data transfer bandwidth and
minimize access latency. Programmable row and column address multiplexing allows a variety of
SDRAM configurations and sizes to be supported without hardware changes.
1.3.13
Enhanced Three-Speed Ethernet Controllers (eTSECs)
The MPC8544E has two on-chip enhanced three-speed Ethernet controllers. The eTSECs incorporate a
media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps Ethernet/802.3
networks with MII, RMII, GMII, RGMII, SGMII, TBI, and RTBI physical interfaces. The eTSECs include
2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.
The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.
Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with
minimal change.
The MPC8544E eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache
to speed classification or other frame processing.
Each eTSEC provides hardware support for accelerating TCP/IP packet transmission and reception. By
default, TCP/IP acceleration is not enabled, and the eTSEC processes frames as pure Ethernet frames.
TCP/IP acceleration can be performed at a number of levels. The eTSEC can parse frames at layer 2 of the
stack only (Ethernet headers and switching headers), layers 2 to 3 (including IP v4 or IP v6), or layers 2
to 4 (including TCP and UDP).
On receive, the eTSEC provides protocol header recognition, header verification (IP v4 header checksum
verification), and TCP/UDP payload checksum verification including verification of associated
pseudo-header checksums. On transmit, the eTSEC provides IP v4 and TCP/UDP header checksum
generation. The eTSEC does not checksum transmitted packets with IP header options or IP fragments.
To provide for quality of service, transmission from up to eight queues is supported with priority-based
queue selection. Arbitration is a modified weighted round-robin queue selection with fair bandwidth
allocation.
On receive, packets may be distributed to any of the 64 virtual receive queues overlaid onto the 8 physical
receive queues. A table-oriented queue filing strategy is provided based on 16 header fields or flags. Frame
rejection is supported for filtering applications.
Filing can be based on Ethernet, IP, and TCP/UDP properties, including VLAN fields, Ether-type, IP
protocol type, IP TOS or differentiated services, IP source and destination addresses, TCP/UDP port
numbers, or user-defined bit fields.
Each eTSEC provides a full-duplex packet FIFO interface port that bypasses the Ethernet MAC, but
re-uses the PHY interface pins. As a result, the FIFO interface normally does not impose the overheads of
Ethernet framing. The FIFO interface operates synchronously, at up to 200MHz, providing up to 3.2-Gbps
full-duplex transfer rates. Bare IP packets, with an optional 32-bit CRC check sequence, can be transferred
to the eTSEC directly. The eTSEC Tx and Rx FIFOs, TCP/IP acceleration functions, and DMA continue
to be used in packet FIFO mode.
There are no mode configuration dependencies between eTSEC1 and eTSEC3.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1-18
Freescale Semiconductor