MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 727
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MPC8544COMEDEV
Manufacturer Part Number
MPC8544COMEDEV
Description
KIT DEV EXPRESS MPC8544COM
Manufacturer
Freescale Semiconductor
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544COMEDEV
Contents
Board
For Use With/related Products
MPC8544
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 14-86
length of the synchronization cycle depends on the relative start of the synchronization process and varies
with every access. It can vary in length from one to n (clock ratio) local bus clocks.
The second column (compensation cycle) of
of LUPWAIT to get in lockstep with the DSI clock. For example, if the clock divider ratio is 1:3 and the
LUPWAIT reaction time is two local bus clocks, because LUPWAIT is synchronized, then one local bus
clock should be inserted.
Freescale Semiconductor
LUPWAIT
DSI_CLK
LGPLy
LCLK
shows an example for a synchronization mechanism for a clock divider of 3. Note that the
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
bst1–bst4
cst1–cst4
redo[0]
redo[1]
amx0
amx1
g0xx
exen
g1tx
g2tx
g3tx
g4t1
g4t3
g5tx
loop
todt
last
uta
na
Sync Cycle
Figure 14-86. UPM Synchronization Cycle
Table 14-45. UPM Synchronization Cycles
1
0
0
0
0
0
0
0
0
0
0
Compensation Cycle
Table 14-45
0
0
0
0
0
0
is intended to compensate for the reaction time
DSI Cycle 1
1
0
12–13
14–15
16–17
20–21
8–11
Bits
0–3
4–7
18
19
22
23
24
25
26
27
28
29
30
31
Local Bus Controller
14-107
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