MPC8544COMEDEV Freescale Semiconductor, MPC8544COMEDEV Datasheet - Page 1321

• Manufacturer Part Number: MPC8544COMEDEV
• Description: KIT DEV EXPRESS MPC8544COM
• Manufacturer: Freescale Semiconductor
• Type: MPUr

Specifications of MPC8544COMEDEV

• Contents: Board
• For Use With/related Products: MPC8544
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EC_GTX_CLK125 (eTSEC gigabit transmit 125 MHz
EC_MDC (eTSEC management data clock) signal, 15-10
EC_MDIO (eTSEC management data input/output, BIDI)
Encryption algorithms, see Security engine (SEC), execution
Error handling
Freescale Semiconductor
signal processing engine (SPE)
software-use SPRs, 6-22
time base
timer registers, 6-14–6-17
DDR, 9-34–9-41, 9-67
DMA, 16-33
DUART, 13-2, 13-22
MMUCSR0 (MMU control and status register 0), 6-32
MSR (machine state register), 6-11
PIDn (process ID registers 0–2), 6-32
PIR (processor ID register), 6-13
PMCn (performance monitor counter registers 0–3),
PMGC0 (performance monitor global control register 0),
PMLCan (performance monitor local control registers
PMLCbn (performance monitor local control registers
PVR (processor version register), 6-13
SPEFSCR (signal processing and embedded
SPRGn (software-use registers 0–7), 6-22
SRR0–1 (save/restore registers 0–1), 6-17
SVR (system version register), 6-14, 19-19
TBL (time base lower register), 6-16
TBU (time base upper register), 6-16
TCR (timer control register), 6-14
TLB0CFG (TLB0 configuration register), 6-33
TLB1CFG (TLB1 configuration register), 6-34
TSR (timer status register), 6-15
UPMCn (user performance monitor counter registers
UPMGC0 (user performance monitor global control
UPMLCan (user performance monitor local control
UPMLCbn (user performance monitor local control
USPRG0 (user software-use register 0), 6-22
XER (integer exception register), 6-8
registers, 6-45
RTC (real time clock) signal options, 4-3, 4-25
source) signal, 15-10
signal, 15-10
units (EUs)
framing error, 13-9, 13-15, 13-21, 13-22
6-52
6-49
a0–a3), 6-50
b0–b3), 6-51
floating-point status and control register), 6-45
0–3), 6-52
register 0), 6-49
registers a0–a3), 6-50
registers b0–b3), 6-51
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ESR (exception syndrome register), see e500 core, registers
eTSEC
ECM
eTSEC, 15-155–15-157
I
L2 cache/SRAM
LBC
PCI Express registers, 18-29–18-42
PCI/PCI-X
security engine (SEC), 12-98, 12-103
block diagram, 15-2
buffer descriptors, 15-173–15-179
clocks
configuration of interfaces, 15-179–15-209
data width (POR), 4-19
error-handling, 15-155–15-157
eTSEC1 protocol (POR), 4-19
eTSEC3 protocol (POR), 4-20
features, 15-2
FIFO interface connections, 15-137
2
C interface
overrun error, 13-22
parity error, 13-22
error handling registers, 8-6–8-9
boot sequencer mode, 11-19
error handling registers, 7-17
error injection, 7-18
transfer error registers, 14-24–14-29
address/data parity, 17-54, 17-65, 17-66
reporting, 17-65–17-66
retry transactions, 17-53
target-abort, 17-53
target-disconnect, 17-53
receive buffer descriptors (RxBD), 15-177
transmit buffer descriptors (TxBD), 15-174
inputs and outputs, 15-9
management clock out (EC_MDC), 15-10, 15-74
operation, 4-25
8-bit FIFO mode, 15-204
GMII interface mode, 15-184
MAC configuration, 15-65
MII interface mode, 15-180
RGMII interface mode, 15-192
RMII interface mode, 15-196
RTBI interface mode, 15-200
TBI interface mode, 15-188
8-bit encoded packet FIFO mode, 15-140
8-bit GMII-style packet FIFO mode, 15-139
CRC appending and checking, 15-138
flow control, 15-138
signal summary, 15-140
PERR and SERR signals, 17-66
target-initiated termination, 17-53
Index-5